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Start condition generation
SCL
(master output)
SDA
(master output)
SDA
[5]
(slave output)
IRIC
IRTR
ICDR
*
Incorrect
Normal
operation
operation
User processing
[4] BBSY set to 1
SCP cleared to 0
(start condition
issuance)
Note: * Data write timing in ICDR
Figure 17.7 Master Transmit Mode Operation Timing Example
17.5.3
Master Receive Operation
The data buffer of the IIC module can receive data consecutively since it consists of ICDRR and
ICDRS. However, if the completion of receiving the last data is delayed, there will be a conflict
between the instruction to issue a stop condition and the SCl clock output to receive the next data.
This may generate unnecessary clocks or fix the output level of the SDA line as low.
The switch timing of the ACKB bit in ICSR should be controlled because the acknowledge bit
does not return an acknowledge signal after receiving the last data in master mode.
These problems can be avoided by using the WAIT function. Follow the procedure shown below.
2
In I
C bus format master receive mode, the master device outputs the receive clock, receives data,
and returns an acknowledge signal. The slave device transmits data. The reception procedure and
operations for sequential data reception with the wait function in synchronization with the ICDR
read operation are shown below.
1
2
3
4
Bit 7
Bit 6
Bit 5
Bit 4
Slave address
Address + R/W
[6] IRIC clear
[6] ICDR write
(MLS = WAIT = 0)
Section 17 I
5
6
7
8
9
Bit 3
Bit 2
Bit 1
Bit 0
[7]
R/W
A
Rev. 3.00 Jan 25, 2006 page 519 of 872
2
C Bus Interface (IIC)
1
2
Bit 7
Bit 6
Data 1
Data 1
[9] IRIC clear
[9] ICDR write
REJ09B0286-0300
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