Figure 15.5 Master Transmit Mode Operation Timing (1); Figure 15.6 Master Transmit Mode Operation Timing (2) - Renesas H8 Series Hardware Manual

2
Section 15 I C Bus Interface 2 (IIC2)
SCL
(Master output)
SDA
(Master output)
SDA
(Slave output)
TDRE
TEND
ICDRT
ICDRS
User
[2] Instruction of start
processing
condition issuance

Figure 15.5 Master Transmit Mode Operation Timing (1)

SCL
(Master output)
SDA
(Master output)
SDA
(Slave output)
TDRE
TEND
ICDRT
ICDRS
User
[5] Write data to ICDRT
processing

Figure 15.6 Master Transmit Mode Operation Timing (2)

Rev. 3.00 Sep. 14, 2006 Page 256 of 408
REJ09B0105-0300
1 2 3 4
Bit 7 Bit 6 Bit 5 Bit 4
Slave address
Address + R/W
Address + R/W
[3] Write data to ICDRT (first byte)
9 1 2 3
Bit 7 Bit 6 Bit 5
A
Data n
5 6 7 8
Bit 3 Bit 2 Bit 1 Bit 0
R/W
[4] Write data to ICDRT (second byte)
4 5 6
Bit 4 Bit 3 Bit 2 Bit 1
Data n
[6] Issue stop condition. Clear TEND.
9 1
Bit 7 Bit 6
A
Data 1
Data 1
[5] Write data to ICDRT (third byte)
7 8 9
Bit 0
A/A
[7] Set slave receive mode
2
Data 2