Figure 17.5 Operation Timing In Master Transmit Mode (1); Figure 17.6 Operation Timing In Master Transmit Mode (2) - Renesas H8S/2437 Hardware Manual

SCL
(master output)
SDA
(master output)
SDA
(slave output)
TDRE
TEND
ICDRT
ICDRS
User
[2] Instruction of start
processing
condition issuance

Figure 17.5 Operation Timing in Master Transmit Mode (1)

SCL
(master output)
SDA
(master output)
SDA
(slave output)
TDRE
TEND
ICDRT
ICDRS
User
[5] Write data to ICDRT.
processing

Figure 17.6 Operation Timing in Master Transmit Mode (2)

1 2 3 4
Bit 7 Bit 6 Bit 5 Bit 4
Slave address
Address + R/
Address + R/
[3] Write data to ICDRT (first byte).
9 1 2 3
Bit 7 Bit 6 Bit 5
A
Data n
5 6 7 8
Bit 3 Bit 2 Bit 1 Bit 0
R/
[4] Write data to ICDRT (second byte).
4 5 6
Bit 4 Bit 3 Bit 2 Bit 1
Data n
[6] Issue stop condition. Clear TEND.
9 1
Bit 7
A
Data 1
Data 1
[5] Write data to ICDRT (third byte).
7 8 9
Bit 0
A/
[7] Set slave receive mode.
Rev. 1.00, 09/03, page 493 of 704
2
Bit 6
Data 2