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7.4.14
DMAC States in Reset State, Standby Modes, and Sleep Mode
When the chip is reset or enters software standby mode, the DMAC is initialized and halts.
DMAC operations continue in sleep mode. Figure 7.24 shows the timing of a cycle-steal transfer
in sleep mode.
CPU cycle
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2
φ
Address bus
RD
HWR LWR
,
Figure 7.24 Timing of Cycle-Steal Transfer in Sleep Mode
DMAC cycle
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T
T
T
T
d
1
2
1
2
Section 7 DMA Controller
Sleep mode
DMAC cycle
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T
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d
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2
1
Rev. 4.00 Jan 26, 2006 page 261 of 938
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REJ09B0276-0400
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