Table 13.5 Flags And Transfer States (Slave Mode) - Renesas H8S/2111B Hardware Manual

Bit single-chip microcomputer h8s family / h8s/2100 series
Table of Contents

Advertisement

Table 13.5 Flags and Transfer States (Slave Mode)

MST
TRS
ESTP
BBSY
0
0
0
0
0
0
1↑
0
0
1↑/0
1
0
1
*
0
0
1
0
0
1↑/0
1
0
1
*
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
0
0
1
0
AL
IRTR
STOP
AASX
0
0
0
0
0
0
0↓
0
0
0
0
0
0
0
0
1↑
1↑
0
0
1↑/0
1
*
0
0↓
0
0
0↓
0
1↑/0
0
2
*
0
1↑/0
2
*
0
0↓
AAS
ADZ
ACKB
ICDRF
0
0
0
0
0
0
1↑
0
0
1↑
1↑
1↑
0
1↑
0
0
0
1↑
0
1↑
0
0
0↓
0
0
1
0
0↓
0
0
0
0
0
1↑
0↓
0↓
0↓
Rev. 1.00, 05/04, page 295 of 544
State
ICDRE
0
Idle state (flag
clearing required)
1↑
Start condition
detected
1
SAR match in first
frame
(SARX≠SAR)
1
General call
address match in
first frame
(SARX≠H'00)
1
SARS match in first
frame
(SAR≠SARX)
Transmission end
(ACKE=1 and
ACKB=1)
1↑
Transmission end
with ICDRE=0
0↓
ICDR write with the
above state
1
Transmission end
with ICDRE=1
0↓
ICDR write with the
above state
1↑
Automatic data
transfer from
ICDRT to ICDRS
with the above
state
Reception end with
ICDRF=0
ICDR read with the
above state

Advertisement

Table of Contents
loading

This manual is also suitable for:

Hd64f2111b

Table of Contents