Transfer Modes; Single Transfer Mode; Single Transfer Example 1; Single Transfer Example 2 - Renesas NU85E Preliminary User's Manual

7.8 Transfer Modes

7.8.1 Single transfer mode

In single transfer mode, the DMAC releases the bus after each byte, halfword, or word transfer. If there is a
subsequent DMA transfer request, a single transfer is performed again. This operation continues until a terminal
count occurs.
If a higher priority DMA transfer request is generated while the DMAC has released the bus, the higher priority
DMA transfer request always takes precedence. However, if a lower priority DMA transfer request is generated
within one clock after the end of a single transfer, even if the previous higher priority DMA transfer request signal
stays active, this request is not prioritized, and the next DMA transfer after the bus is released for the CPU is a
transfer based on the newly generated, lower priority DMA transfer request.
Figures 7-12 to 7-15 show examples for single transfer.
DMARQ3
(Input)
CPU CPU DMA3 CPU DMA3
Note The bus is always released.
Figure 7-13 shows a single transfer mode example in which a higher priority DMA transfer request is generated.
DMA channels 0 to 2 are used for a block transfer, and channel 3 is used for a single transfer.
DMARQ0
(Input)
DMARQ1
(Input)
DMARQ2
(Input)
DMARQ3
(Input)
CPU CPU CPU DMA3 CPU
Note The bus is always released.
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CHAPTER 7 DMAC
Figure 7-12. Single Transfer Example 1
Note Note Note
CPU DMA3 CPU
Figure 7-13. Single Transfer Example 2
Note Note
DMA0 DMA0 CPU DMA1
DMA channel 0
terminal count
Preliminary User's Manual A14874EJ3V0UM
CPU CPU CPU CPU CPU DMA3
Note
DMA1 CPU DMA2 DMA2 CPU DMA3
DMA channel 1
terminal count
DMA channel 2
terminal count
Note
CPU DMA3 CPU CPU CPU
DMA channel 3 terminal count
Note
CPU DMA3
DMA channel 3
terminal count