Table 13.4 Flags And Transfer States (Master Mode) - Renesas H8S/2111B Hardware Manual

Bit single-chip microcomputer h8s family / h8s/2100 series
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Table 13.4 Flags and Transfer States (Master Mode)

MST
TRS
ESTP
BBSY
1
1
0
0
1
1
1↑
0
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0↓
0↓
1
0
1
0↓
0
[Legend]
0:
0-state retained
1:
1-state retained
—:
Previous state retained
0
:
Cleared to 0
1
:
Set to 1
Rev. 1.00, 05/04, page 294 of 544
AL
IRTR
STOP
AASX
0
0
0↓
0
0
1↑
0
0
0
0
0
0
0
0
0
1↑
0
0
0
0
0
0
0
0
0
0
0
0
1↑
0
0
0
1↑
0
0
0
0
0
0
0
0
0
0
0
0
1↑
0
0
0
0
1↑
0
0
0
AAS
ADZ
ACKB
ICDRF
0↓
0↓
0
0
0
0
0
0
0
0
1↑
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1↑
0
0
0↓
0
0
1
0
0
0↓
0
0
1↑
0
0
0
0
State
ICDRE
0
Idle state (flag
clearing required)
1↑
Start condition
detected
Wait state
Transmission end
(ACKE=1 and
ACKB=1)
1↑
Transmission end
with ICDRE=0
0↓
ICDR write with the
above state
1
Transmission end
with ICDRE=1
0↓
ICDR write with the
above state or after
start condition
detected
1↑
Automatic data
transfer from
ICDRT to ICDRS
with the above
state
Reception end with
ICDRF=0
ICDR read with the
above state
Reception end with
ICDRF=1
ICDR read with the
above state
Automatic data
transfer from
ICDRS to ICDRR
with the above
state
Arbitration lost
0↓
Stop condition
detected

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