C Bus Control Register (Iccr) - Renesas H8S/2100 Series Hardware Manual

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18.3.5 I

C Bus Control Register (ICCR)

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ICCR controls the I C bus interface and performs interrupt flag confirmation.
Bit Bit Name
7 ICE
6 IEIC
5 MST
4 TRS
Initial
Value R/W Description
2
0 R/W I
0: I
1: I
2
0 R/W I
0: Disables interrupts from the I
1: Enables interrupts from the I
0 R/W Master/Slave Select
0 R/W Transmit/Receive Select
MST TRS
Both these bits will be cleared by hardware when they
lose in a bus contention in master mode with the I
bus format. In slave receive mode with I
the R/W bit in the first frame immediately after the start
condition sets these bits in receive mode or transmit
mode automatically by hardware.
Modification of the TRS bit during transfer is deferred
until transfer is completed, and the changeover is made
after completion of the transfer (at the rising edge of
the 9th clock).
C Bus Interface Enable
2
C bus interface modules are stopped and I
interface module internal state is initialized. SAR
and SARX can be accessed.
2
C bus interface modules can perform transfer
operation, and the ports function as the SCL and
SDA input/output pins. ICMR and ICDR can be
accessed.
C Bus Interface Interrupt Enable
CPU
CPU.
0 0: Slave receive mode
0 1: Slave transmit mode
1 0: Master receive mode
1 1: Master transmit mode
Rev. 1.00 Apr. 28, 2008 Page 543 of 994
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Section 18 I C Bus Interface (IIC)
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2
C bus interface to the
2
C bus interface to the
2
C bus format,
REJ09B0452-0100
C bus
2
C