Bus Control Register (Bcr) - Renesas H8S/2368 Series Hardware Manual

6.3.7

Bus Control Register (BCR)

BCR is used for idle cycle settings, selection of the external bus released state protocol, enabling
or disabling of the write data buffer function, and enabling or disabling of WAIT pin input.
Bit
Bit Name
15 BRLE
14 BREQOE
−
13
12 IDLC
11 ICIS1
Initial Value R/W
0 R/W
0 R/W
0 R/W
1 R/W
1 R/W
Description
External Bus Release Enable
Enables or disables external bus release.
0: External bus release disabled
BREQ, BACK, and BREQO pins can be used
as I/O ports
1: External bus release enabled
BREQO Pin Enable
Controls outputting the bus request signal
(BREQO) to the external bus master in the
external bus released state, when an internal
bus master performs an external address space
access, or when a refresh request is generated.
0: BREQO output disabled
BREQO pin can be used as I/O port
1: BREQO output enabled
Reserved
Though this bit can be read from or written to,
the write value should always be 0.
Idle Cycle State Number Select
Specifies the number of states in the idle cycle
set by ICIS2, ICIS1, and ICIS0.
0: Idle cycle comprises 1 state
1: Idle cycle comprises 2 states
Idle Cycle Insert 1
When consecutive external read cycles are
performed in different areas, an idle cycle can
be inserted between the bus cycles.
0: Idle cycle not inserted
1: Idle cycle inserted
Rev. 2.00, 05/03, page 121 of 820