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Bits 2 to 0—Bit Counter (BC2 to BC0): Bits BC2 to BC0 specify the number of bits to be
transferred next. With the I
the data is transferred with one addition acknowledge bit. Bit BC2 to BC0 settings should be made
during an interval between transfer frames. If bits BC2 to BC0 are set to a value other than 000,
the setting should be made while the SCL line is low.
The bit counter is initialized to 000 by a reset and when a start condition is detected. The value
returns to 000 at the end of a data transfer, including the acknowledge bit.
Bit 2
Bit 1
Bit 0
BC2
BC1
BC0
0
0
0
1
1
0
1
1
0
0
1
1
0
1
2
18.2.5
I
C Bus Control Register (ICCR)
Bit
:
7
ICE
Initial value :
0
R/W
:
R/W
Note: * Only 0 can be written, for flag clearing.
ICCR is an 8-bit readable/writable register that enables or disables the I
disables interrupts, selects master or slave mode and transmission or reception, enables or disables
acknowledgement, confirms the I
performs interrupt flag confirmation.
ICCR is initialized to H'01 by a reset and in hardware standby mode.
812
2
C bus format (when the FS bit in SAR or the FSX bit in SARX is 0),
Synchronous Serial Format
8
1
2
3
4
5
6
7
6
5
IEIC
MST
0
0
R/W
R/W
2
C bus interface bus status, issues start/stop conditions, and
Bits/Frame
2
I
C Bus Format
9
2
3
4
5
6
7
8
4
3
TRS
ACKE
BBSY
0
0
R/W
R/W
R/W
(Initial value)
2
1
0
SCP
IRIC
0
0
1
R/(W)*
W
2
C bus interface, enables or
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