C Bus Control Register (Iccr) - Renesas Hitachi H8S/2194 Series Hardware Manual

2
25.2.5 I

C Bus Control Register (ICCR)

7
Bit :
ICE
Initial value : 0
R/W : R/W
Note: * Only 0 can be written to clear the flag.
ICCR is an 8-bit readable/writable register that enables or disables the I
or disables interrupts, selects master or slave mode and transmission or reception, enables or
disables acknowledgement, confirms the I
and performs interrupt flag confirmation.
ICCR is initialized to H'01 by a reset.
2
Bit 7: I C Bus Interface Enable (ICE)
Selects whether or not the I
function as SCL and SDA input/output pins and transfer operations are enabled. When ICE is
2
cleared to 0, the I C bus interface module is disabled, and the internal state is initialized.
The SAR and SARX registers can be accessed when ICE is 0. The ICMR and ICDR registers
can be accessed when ICE is 1.
Bit 7
ICE Description
2
0 I C bus interface module disabled, with SCL and SDA signal pins set to port function
SAR and SARX can be accessed. The internal state of the I
is initialized.
2
1 I C bus interface module enabled for transfer operations (pins SCL and SCA are
driving the bus)
ICMR and ICDR can be accessed
2
Bit 6: I C Bus Interface Interrupt Enable (IEIC)
Enables or disables interrupts from the I
Bit 6
IEIC Description
0 Interrupts disabled
1 Interrupts enabled
6 5
IEIC MST TRS
0 0
R/W R/W R/W
2
C bus interface bus status, issues start/stop conditions,
2
C bus interface is to be used. When ICE is set to 1, port pins
2
C bus interface to the CPU.
4 3 2
ACKE BBSY
0 0 0
R/W R/W
Rev. 2.0, 11/00, page 531 of 1037
1 0
IRIC SCP
0 1
R/(W) *
W
2
C bus interface, enables
2
C bus interface module
(Initial value)
(Initial value)