Bus Control Register (Bcr) - Renesas H8/3067 Series User Manual

Section 6 Bus Controller
6.2.5

Bus Control Register (BCR)

7
Bit
ICIS1
Initial value 1
Read/Write R/W
BCR is an 8-bit readable/writable register that enables or disables idle cycle insertion, selects the
area division unit, and enables or disables WAIT pin input.
BCR is initialized to H'C6 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—Idle Cycle Insertion 1 (ICIS1): Selects whether one idle cycle state is to be inserted
between bus cycles in case of consecutive external read cycles for different areas.
Bit 7
ICIS1 Description
0 No idle cycle inserted in case of consecutive external read cycles for different
areas
1 Idle cycle inserted in case of consecutive external read cycles for different
areas
Bit 6—Idle Cycle Insertion 0 (ICIS0): Selects whether one idle cycle state is to be inserted
between bus cycles in case of consecutive external read and write cycles.
Bit 6
ICIS0 Description
0 No idle cycle inserted in case of consecutive external read and write cycles
1 Idle cycle inserted in case of consecutive external read and write cycles
Bit 5—Burst ROM Enable (BROME): Selects whether area 0 is a burst ROM interface area.
Bit 5
BROME Description
0 Area 0 is a basic bus interface area
1 Area 0 is a burst ROM interface area
Rev. 4.00 Jan 26, 2006 page 132 of 938
REJ09B0276-0400
6 5
ICIS0 BROME BRSTS1
1 0
R/W R/W
4 3
BRSTS0
0 0
R/W R/W
2 1
— RDEA WAITE
1 1
— R/W
(Initial value)
(Initial value)
(Initial value)
0
0
R/W