Internal Clock Source (Ics) - NXP Semiconductors MC9S08SU16 Reference Manual

• BUSCLK — Bus clock is the clock source for all peripherals and flash module
• HSCLK — High speed clock is up to 40 MHz. It can be set to 1:1 bus clock or
2:1 bus clock. It does not support other clock ratio. it can be selected as the clock
source to the PWM and PDB
After reset, ICSOUTCLK clock is around 20 MHz.
• ICSLCLK — This clock source is derived from the digitally controlled oscillator
(DCO) of the ICS when the ICS is configured to run off of the internal or external
reference clock. Development tools can select this internal self-clocked source (20
MHz) to speed up BDC communications in systems where the bus clock is slow.
• ICSIRCLK — This is the internal reference clock and can be selected as the clock
source to the WCOP module.
• ICSFFCLK — This generates the fixed frequency clock (FFCLK) after being
synchronized to the bus clock. It can be selected as clock source, after being divided
by 2, to the FTM and MTIM modules. The frequency of the ICSFFCLK is
determined by the setting of the ICS.
• LPOCLK — This clock is generated from an internal low power oscillator (≈20 kHz)
that is completely independent of the ICS module. The LPOCLK can be selected as
the clock source to the WCOP module.
• TCLK — This is an optional external clock source for the FTM and MTIM and
PWT0 and PWT1 modules. The TCLK must be limited to 1/4th frequency of the bus
clock for synchronization.
• CLKOUT — This clock is a buffered bus clock to a package pin.
• CLKIN — This is an external clock input from package pins. This clock input cannot
be dynamically switched between its inputs (DC - 40 MHz).

5.3 Internal clock source (ICS)

The internal clock source (ICS) module provides clock source options for the MCU. The
module contains a frequency-locked loop (FLL) as a clock source that is controllable by
an internal or external reference clock. The module can provide this FLL clock or the
internal reference clock as a source for the MCU system clock, ICSCLK.
Whichever clock source is chosen, ICSCLK is the output from a bus clock divider
(BDIV), which allows a lower clock frequency to be derived.
Key features of the ICS module are:
• Frequency-locked loop (FLL) is trimmable for accuracy
NXP Semiconductors
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 5 Clock management
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