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On-chip debug system (DBG)
27.3.3 Change-of-flow information
To minimize the amount of information stored in the FIFO, only information related to
instructions that cause a change to the normal sequential execution of instructions is
stored. With knowledge of the source and object code program stored in the target
system, an external debugger system can reconstruct the path of execution through many
instructions from the change-of-flow information stored in the FIFO.
For conditional branch instructions where the branch is taken (branch condition was
true), the source address is stored (the address of the conditional branch opcode). Because
BRA and BRN instructions are not conditional, these events do not cause change-of-flow
information to be stored in the FIFO.
Indirect JMP and JSR instructions use the current contents of the H:X index register pair
to determine the destination address, so the debug system stores the run-time destination
address for any indirect JMP or JSR. For interrupts, RTI, or RTS, the destination address
is stored in the FIFO as change-of-flow information.
27.3.4 Tag vs. force breakpoints and triggers
Tagging is a term that refers to identifying an instruction opcode as it is fetched into the
instruction queue, but not taking any other action until and unless that instruction is
actually executed by the CPU. This distinction is important because any change-of-flow
from a jump, branch, subroutine call, or interrupt causes some instructions that have been
fetched into the instruction queue to be thrown away without being executed.
A force-type breakpoint waits for the current instruction to finish and then acts upon the
breakpoint request. The usual action in response to a breakpoint is to go to active
background mode rather than continuing to the next instruction in the user application
program.
The tag vs. force terminology is used in two contexts within the debug module. The first
context refers to breakpoint requests from the debug module to the CPU. The second
refers to match signals from the comparators to the debugger control logic. When a tag-
type break request is sent to the CPU, a signal is entered into the instruction queue along
with the opcode so that if/when this opcode ever executes, the CPU will effectively
replace the tagged opcode with a BGND opcode so the CPU goes to active background
mode rather than executing the tagged instruction. When the TRGSEL control bit in the
DBGT register is set to select tag-type operation, the output from comparator A or B is
qualified by a block of logic in the debug module that tracks opcodes and produces only a
trigger to the debugger if the opcode at the compare address is actually executed. There is
separate opcode tracking logic for each comparator so more than one compare event can
be tracked through the instruction queue at a time.
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
540
NXP Semiconductors
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