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Programmer's Model and CPU Registers
10.2.4 Program Counter (PC)
The program counter is a 16-bit register that contains the address of the next instruction
or operand to be fetched.
During normal program execution, the program counter automatically increments to the
next sequential memory location every time an instruction or operand is fetched. Jump,
branch, interrupt, and return operations load the program counter with an address other
than that of the next sequential location. This is called a change-of-flow.
During reset, the program counter is loaded with the reset vector that is located at
0xFFFE and 0xFFFF. The vector stored there is the address of the first instruction that
will be executed after exiting the reset state.
10.2.5 Condition Code Register (CCR)
The 8-bit condition code register contains the interrupt mask (I) and five flags that
indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to 1.
The following paragraphs describe the functions of the condition code bits in general
terms.
Field
Description
7
Two's Complement Overflow Flag — The CPU sets the overflow flag when a two's complement
overflow occurs. The signed branch instructions BGT, BGE, BLE, and BLT use the overflow flag.
V
0 No overflow
1 Overflow
4
Half-Carry Flag — The CPU sets the half-carry flag when a carry occurs between accumulator bits
3 and 4 during an add-without-carry (ADD) or add-with-carry (ADC) operation. The half-carry flag is
H
required for binary-coded decimal (BCD) arithmetic operations. The DAA instruction uses the states
of the H and C condition code bits to automatically add a correction value to the result from a
previous ADD or ADC on BCD operands to correct the result to a valid BCD value.
0 No carry between bits 3 and 4
1 Carry between bits 3 and 4
Interrupt Mask Bit — When the interrupt mask is set, all maskable CPU interrupts are disabled.
3
CPU interrupts are enabled when the interrupt mask is cleared. When a CPU interrupt occurs, the
I
interrupt mask is set automatically after the CPU registers are saved on the stack, but before the
first instruction of the interrupt service routine is executed.
Interrupts are not recognized at the instruction boundary after any instruction that clears I (CLI or
TAP). This ensures that the next instruction after a CLI or TAP will always be executed without the
possibility of an intervening interrupt, provided I was set.
0 Interrupts enabled
130
Table 10-1. CCR Register Field Descriptions
Table continues on the next page...
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
NXP Semiconductors
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