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It is possible to use the output compare mode with (ELSnB:ELSnA = 0:0). In this case,
when the counter reaches the value in the CnVH:CnVL registers, the CHnF bit is set and
the channel (n) interrupt is generated, if CHnIE = 1. However, the channel (n) output is
not modified and controlled by FTM.
19.5.6 Edge-aligned PWM (EPWM) mode
The edge-aligned mode is selected when all of the following apply:
• (CPWMS = 0)
• (MSnB = 1)
The EPWM period is determined by (MODH:L + 0x0001) and the pulse width (duty
cycle) is determined by (CnVH:L).
The CHnF bit is set and the channel (n) interrupt is generated (if CHnIE = 1) at the
channel (n) match (FTM counter = CnVH:L), that is, at the end of the pulse width.
This type of PWM signal is called edge-aligned because the leading edges of all PWM
signals are aligned with the beginning of the period, which is the same for all channels
within an FTM.
counter overflow
channel (n) output
Figure 19-11. EPWM period and pulse width with ELSnB:ELSnA = 1:0
If (ELSnB:ELSnA = 0:0) when the counter reaches the value in the CnVH:L registers,
the CHnF bit is set and the channel (n) interrupt is generated (if CHnIE = 1), however,
the channel (n) output is not controlled by FTM.
If (ELSnB:ELSnA = 1:0), then the channel (n) output is forced high at the counter
overflow, when the value of 0x0000 is loaded into the FTM counter. Additionally, it is
forced low at the channel (n) match, when the FTM counter = CnVH:L. See the
following figure.
NXP Semiconductors
counter overflow
period
pulse
width
channel (n) match
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 19 FlexTimer Module (FTM)
counter overflow
channel (n) match
channel (n) match
335
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