Port Filter Register 2 (Port_Ioflt2) - NXP Semiconductors MC9S08SU16 Reference Manual

8.5.14 Port Filter Register 2 (PORT_IOFLT2)

This register sets the filters for input from PWT, I2C and XB.
Address: 0h base + 18EFh offset = 18EFh
Bit 7
Read
FLTPWT1
Write
Reset
0
Field
7–6 Filter Selection For Input from PWT1
FLTPWT1
00 No filter
01 FLTDIV1
10 FLTDIV2
11 BUSCLK
5–4 Filter Selection For Input from PWT0
FLTPWT0
00 No filter
01 FLTDIV1
10 FLTDIV2
11 BUSCLK
3–2 Filter Selection For Input from SDA and SCL.
FLTI2C
00 No filter
01 FLTDIV1
10 FLTDIV2
11 BUSCLK
FLTXBI Filter Selection For Input from XB_IN0 and XB_IN1
00 No filter
01 FLTDIV1
10 FLTDIV2
11 FLTDIV3
NXP Semiconductors
6 5
FLTPWT0
0 0
PORT_IOFLT2 field descriptions
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
4 3
FLTI2C
0 0
Description
Chapter 8 Port Control (PORT)
2 1
FLTXBI
0 0
0
0
95