Table of Contents
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Section number
3.3
Register addresses assignments.................................................................................................................................... 46
3.4
Random-access memory (RAM).................................................................................................................................. 51
3.5
Flash memory................................................................................................................................................................51
3.6
System register file....................................................................................................................................................... 52
4.1
Interrupts....................................................................................................................................................................... 53
4.1.1
Interrupt stack frame...................................................................................................................................... 54
4.1.2
Hardware nested interrupt.............................................................................................................................. 55
4.1.2.1
4.1.2.2
4.1.2.3
4.1.2.4
4.2
IPC memory map and register descriptions.................................................................................................................. 59
4.2.1
IPC Status and Control Register (IPC_SC)....................................................................................................59
4.2.2
Interrupt Priority Mask Pseudo Stack Register (IPC_IPMPS)...................................................................... 60
4.2.3
Interrupt Level Setting Registers n (IPC_ILRSn)..........................................................................................61
4.3
IRQ................................................................................................................................................................................61
4.3.1
Features.......................................................................................................................................................... 62
4.3.1.1
4.3.1.2
4.4
IRQ Memory Map and Register Descriptions.............................................................................................................. 63
4.4.1
Interrupt Pin Request Status and Control Register (IRQ_SC)....................................................................... 63
5.1
Clock module................................................................................................................................................................ 65
5.2
System clock distribution..............................................................................................................................................65
5.3
Internal clock source (ICS)........................................................................................................................................... 67
5.4
20 kHz low-power oscillator (LPO)............................................................................................................................. 68
4
Chapter 4
Interrupt priority level register................................................................................................... 57
Interrupt priority level comparator set....................................................................................... 57
Interrupt priority mask update and restore mechanism..............................................................57
Integration and application of the IPC....................................................................................... 58
Configuration options................................................................................................................ 62
Edge and level sensitivity.......................................................................................................... 63
Chapter 5
Title
Interrupt
Page
NXP Semiconductors
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