Debug Status Register (Dbg_S) - NXP Semiconductors MC9S08SU16 Reference Manual

Memory map and registers

28.3.15 Debug Status Register (DBG_S)

The figure shows the values in POR or non-end-run reset. The
bits of AF, BF and CF are undefined and ARMF is reset to 0 in
end-run reset. In the case of an end-trace to reset where
DBGEN=1 and BEGIN=0, ARMF gets cleared by reset but AF,
BF, and CF do not change after reset.
Address: 18C0h base + Eh offset = 18CEh
Bit 7
Read AF
Write
Reset
0
Field
7 Trigger A Match Bit
AF
The AF bit indicates if Trigger A match condition was met since arming.
0 Comparator A did not match.
1 Comparator A match.
6 Trigger B Match Bit
BF
The BF bit indicates if Trigger B match condition was met since arming.
0 Comparator B did not match.
1 Comparator B match.
5 Trigger C Match Bit
CF
The CF bit indicates if Trigger C match condition was met since arming.
0 Comparator C did not match.
1 Comparator C match.
4–1 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
0 Arm Flag Bit
ARMF
The ARMF bit indicates whether the debugger is waiting for trigger or waiting for the FIFO to fill. While
DBGEN = 1, this status bit is a read-only image of the ARM bit in DBGC.
0 Debugger not armed.
1 Debugger armed.
564
NOTE
6 5
BF CF
0 0
DBG_S field descriptions
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
4 3
0
0 0
Description
2 1
ARMF
0 0
NXP Semiconductors
0
1