Clamp Control Register (Gdu_Clmpctrl) - NXP Semiconductors MC9S08SU16 Reference Manual

Field
0 Interrupt disabled.
1 Interrupt enabled.
2 Analog Comparator Flag Rising
CFR
During normal operation, the CFR bit is set when a rising edge on COUT has been detected. The CFR bit
is cleared by writing a logic one to the bit.
0 Rising edge on COUT has not been detected.
1 Rising edge on COUT has occurred.
1 Analog Comparator Flag Falling
CFF
During normal operation, the CFF bit is set when a falling edge on COUT has been detected. The CFF bit
is cleared by writing a logic one to the bit.
0 Falling edge on COUT has not been detected.
1 Falling edge on COUT has occurred.
0 Analog Comparator Output
COUT
Reading the COUT bit will return the current value of the analog comparator output. The register bit is
reset to zero and will read as CR1[INV] when the Analog Comparator module is disabled (CR1[EN] = 0).
Writes to this bit are ignored.

25.6.13 Clamp Control Register (GDU_CLMPCTRL)

Address: 20h base + 1850h offset = 1870h
Bit 7
Read
OVPEN
Write
Reset 1
Field
7 Overvoltage Protection Enable
OVPEN
0 Disables the overvoltage protection (OVP).
1 Enables the OVP.
6 Overvoltage Protection Interrupt Enable
OVPIE
0 Disables the OVP interrupt.
1 Enables the OVP interrupt.
5–4 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
3–1 Tunes the clamped output voltage when the clamp works at regulation mode. The tuning range is 5 V
TUNE ±20% with step of 5%.
0 Clamp Enable
CLAMPEN
NXP Semiconductors
GDU_PHCMP2SCR field descriptions (continued)
6 5
0
OVPIE
0 0
GDU_CLMPCTRL field descriptions
Table continues on the next page...
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Description
4 3
TUNE
0 0
Description
Chapter 25 Gate Drive Unit (GDU)
2 1
CLAMPEN
1 1
0
0
449