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The CHnF bit is set and channel (n) interrupt is generated (if CHnIE = 1) at the channel
(n) match (FTM counter = CnVH:L) when the FTM counting is down, at the begin of the
pulse width, and when the FTM counting is up, at the end of the pulse width.
This type of PWM signal is called center-aligned because the pulse width centers for all
channels are aligned with the value of 0x0000.
The other channel modes are not compatible with the up-down counter (CPWMS = 1).
Therefore, all FTM channels must be used in CPWM mode when (CPWMS = 1).
counter overflow
FTM counter =
channel (n) output
Figure 19-14. CPWM period and pulse width with ELSnB:ELSnA = 1:0
If (ELSnB:ELSnA = 0:0) when the counter reaches the value in the CnVH:L registers,
the CHnF bit is set and the channel (n) interrupt is generated (if CHnIE = 1), however the
channel (n) output is not controlled by FTM.
If (ELSnB:ELSnA = 1:0), then the channel (n) output is forced high at the channel (n)
match (FTM counter = CnVH:L) when counting down, and it is forced low at the channel
(n) match when counting up; see the following figure.
MODH:L = 0x0008
CnVH:L = 0x0005
...
CNTH:L
channel (n) output
CHnF bit
TOF bit
Figure 19-15. CPWM signal with ELSnB:ELSnA = 1:0
If (ELSnB:ELSnA = X:1), then the channel (n) output is forced low at the channel (n)
match (FTM counter = CnVH:L) when counting down, and it is forced high at the
channel (n) match when counting up; see the following figure.
NXP Semiconductors
channel (n) match
(FTM counting
is down)
MODH:L
counter
overflow
channel (n) match in
down counting
7
7
5
4
3
8
6
previous value
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
FTM counter =
0x0000
channel (n) match
(FTM counting
is up)
pulse width
2 x (CnVH:L)
period
2 x (MODH:L)
channel (n) match in
up counting
2
1
1
2
3
4
0
Chapter 19 FlexTimer Module (FTM)
counter overflow
FTM counter =
MODH:L
counter
overflow
channel (n) match in
down counting
5
7
7
6
8
6
5
...
337
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