NXP Semiconductors MC9S08LG32 Reference Manual
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NXP Semiconductors MC9S08LG32 Reference Manual

NXP Semiconductors MC9S08LG32 Reference Manual

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MC9S08LG32
MC9S08LG16
Reference Manual
T
HIS DOCUMENT CONTAINS INFORMATION ON A NEW PRODUCT UNDER DEVELOPMENT
DISCONTINUE THIS PRODUCT WITHOUT NOTICE
HCS08
Microcontrollers
MC9S08LG32RM
Rev. 5
8/2009
freescale.com
.
. F
REESCALE RESERVES THE RIGHT TO CHANGE OR

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  • Page 1 MC9S08LG32 MC9S08LG16 Reference Manual HIS DOCUMENT CONTAINS INFORMATION ON A NEW PRODUCT UNDER DEVELOPMENT REESCALE RESERVES THE RIGHT TO CHANGE OR DISCONTINUE THIS PRODUCT WITHOUT NOTICE HCS08 Microcontrollers MC9S08LG32RM Rev. 5 8/2009 freescale.com...
  • Page 3 MC9S08LG32 Series Features 8-Bit HCS08 Central Processor Unit (CPU) • On-chip in-circuit emulator (ICE) debug module containing three comparators and nine trigger modes; • Up to 40 MHz CPU at 5.5 V to 2.7 V across temperature eight deep FIFO for storing change-of-flow addresses range of –40 °C to 85 °C and –40 °C to 105 °C...
  • Page 5 Rev. 5 • MC9S08LG32PB (Product Brief) 8/2009 Contains descriptive feature set, example application information, and developer environment details • MC9S08LG32 Data Sheet Contains package information, pinouts, electricals/characterization data, and mechanical drawings Find the most current versions of all documents at: http://www.freescale.com...
  • Page 6 • In Chapter 12, “Inter-Integrated Circuit (S08IICV2),” a note is added in the introduction mentioning that MC9S08LG32 series of MCUs include only one IIC module. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2009. All rights reserved.

  • Page 7: Table Of Contents

    Chapter 15 Real-Time Counter (S08RTCV1) ............297 Chapter 16 Timer/Pulse-Width Modulator (S08TPMV3) ........306 Chapter 17 Modulo Timer (S08MTIMV1) ..............327 Chapter 18 Development Support................337 Chapter 19 Debug Module (DBG) (64K)..............350 MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 9 Contents Section Number Title Page Chapter 1 Device Overview Devices in the MC9S08LG32 Series ....................21 MCU Block Diagram ........................22 System Clock Distribution .......................24 Chapter 2 Pins and Connections Introduction ............................27 Device Pin Assignment ........................27 Recommended System Connections ....................31 2.3.1 Power ..........................33 2.3.2 Oscillator ...........................33...
  • Page 10 Section Number Title Page MC9S08LG32 Series Memory Map ....................49 Reset and Interrupt Vector Assignments ..................50 Register Addresses and Bit Assignments..................52 4.4.1 Reserved Flash Locations ....................59 RAM..............................60 Flash ..............................60 4.6.1 Features ..........................61 4.6.2 Program and Erase Times ....................61 4.6.3 Program and Erase Command Execution .................62 4.6.4 Burst Program Execution ....................63...
  • Page 11 6.7.9 Port I Registers ........................125 Chapter 7 Keyboard Interrupt (S08KBIV2) Introduction ............................128 7.1.1 Module Configuration .....................128 7.1.2 KBI Clock Gating ......................128 7.1.3 Features ...........................130 7.1.4 Modes of Operation ......................130 7.1.5 Block Diagram ........................130 External Signal Description ......................131 MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 12 HCS08 Instruction Set Summary ....................144 Chapter 9 LCD Module (S08LCDLPV1) Introduction ............................158 9.1.1 LCD Clock Sources ......................158 9.1.2 LCD Modes of Operation ....................158 9.1.3 LCD Status after Stop2 Wakeup ..................158 9.1.4 LCD Clock Gating ......................158 MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 13 10.1.1 ADC shared with LCD ....................200 10.1.2 ADC Reference and Supply Voltage ................200 10.1.3 ADC Clock Gating ......................200 10.1.4 Module Configurations ....................201 10.1.5 Features ...........................204 10.1.6 ADC Module Block Diagram ..................204 10.2 External Signal Description ......................205 MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 14 11.1.3 Modes of Operation ......................229 11.2 External Signal Description ......................230 11.3 Register Definition .........................230 11.3.1 ICS Control Register 1 (ICSC1) ..................231 11.3.2 ICS Control Register 2 (ICSC2) ..................233 11.3.3 ICS Trim Register (ICSTRM) ..................233 MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 15 12.4.2 10-bit Address .........................254 12.4.3 General Call Address ......................255 12.5 Resets .............................255 12.6 Interrupts ............................255 12.6.1 Byte Transfer Interrupt ....................255 12.6.2 Address Detect Interrupt ....................256 12.6.3 Arbitration Lost Interrupt ....................256 12.7 Initialization/Application Information ...................257 MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 16 14.2.4 SS — Slave Select ......................283 14.3 Modes of Operation........................284 14.3.1 SPI in Stop Modes ......................284 14.4 Register Definition .........................284 14.4.1 SPI Control Register 1 (SPIxC1) ..................284 14.4.2 SPI Control Register 2 (SPIxC2) ..................285 MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 17 16.1.6 Modes of Operation ......................308 16.1.7 Block Diagram ........................309 16.2 Signal Description ..........................311 16.2.1 Detailed Signal Descriptions ..................311 16.3 Register Definition .........................314 16.3.1 TPM Status and Control Register (TPMxSC) ..............314 16.3.2 TPM-Counter Registers (TPMxCNTH:TPMxCNTL) ............315 MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 18 18.2.2 Communication Details ....................339 18.2.3 BDC Commands ......................343 18.2.4 BDC Hardware Breakpoint .....................345 18.3 Register Definition .........................345 18.3.1 BDC Registers and Control Bits ..................346 18.3.2 System Background Debug Force Reset Register (SBDFR) ..........348 MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 19 19.4 Functional Description ........................365 19.4.1 Comparator ........................365 19.4.2 Breakpoints ........................365 19.4.3 Trigger Selection ......................366 19.4.4 Trigger Break Control (TBC) ..................366 19.4.5 FIFO ..........................370 19.4.6 Interrupt Priority ......................371 19.5 Resets .............................371 19.6 Interrupts ............................371 MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 21: Chapter 1 Device Overview

    HCS08 core and are available with a variety of memory sizes and package types. The MC9S08LG32 series MCUs are targeted to serve automotive, consumer and industrial markets. Please check the ordering part numbers for different qualification tier products in Ordering Information section of MC9S08LG32 Data Sheet.

  • Page 22: Mcu Block Diagram

    Chapter 1 Device Overview MCU Block Diagram The block diagram in Figure 1-1 shows the structure of the MC9S08LG32 series MCU. HCS08 CORE LCD28/ADC5/TPMCLK/PTA7 ON-CHIP ICE (ICE) and LCD27/ADC4/TPM2CH1/KBI7/PTA6 DEBUG MODULE (DBG) LCD26/ADC3/TPM2CH0/KBI6/PTA5 LCD25/ADC2/RX2/KBI5/PTA4 LCD24/ADC1/TX2/KBI4/PTA3 BKGD/MS Real Time Counter LCD23/ADC0/SDA/PTA2...
  • Page 23 Liquid Crystal Display Module (LCD) Low Power Oscillator (XOSC) Modulo Timer (MTIM) On-Chip In-Circuit Debug/Emulator (DBG) Real Time Counter (RTC) Serial Communications Interface (SCI) Serial Peripheral Interface (SPI) Timer Pulse Width Modulator (TPM) MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 24: System Clock Distribution

    This clock source can be used for LCD and RTC in stop2 mode. For more information regarding use of OSCOUT with these modules, see Chapter 15, “Real-Time Counter (S08RTCV1),” and Chapter 9, “LCD Module (S08LCDLPV1).” MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 25 See the ADC chapter and and erase operation. See the exceed one half of the bus clock frequency. electricals appendix for electricals appendix for details. details. Figure 1-2. System Clock Distribution Diagram MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 26 Chapter 1 Device Overview MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 27: Chapter 2 Pins And Connections

    Device Pin Assignment This section shows the pin assignments for MC9S08LG32 series. The priority of functions on a pin is in ascending order from left to right and bottom to top. Another view of pinouts and function priority is given Table 2-1.
  • Page 28 80-Pin LQFP PTA6/KBI7/TPM2CH1/ADC4/LCD27 PTB6/LCD39 PTA7/TPMCLK/ADC5/LCD28 PTB5/LCD38 PTC5/BKGD/MS PTB4/LCD37 PTC6/RESET PTB1/LCD30 PTH0/KBI4/ADC6 PTB0/LCD29 PTH1/KBI5/ADC7 PTD1/LCD1 PTH2KBI6/ADC8 PTD0/LCD0 PTH3/KBI7/ADC9 CAP1 PTH4/RX1/KBI2/TPM1CH1/ADC10 CAP2 PTH5/TX1/KBI3/TPM1CH0/ADC11 PTF3/SS/KBI0/TPM2CH5 Figure 2-1. 80-Pin LDFP NOTE are internally connected to V REFH REFL MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 29 PTD2/LCD2 PTA3/KBI4/TX2/ADC1/LCD24 PTB3/LCD32 64-Pin LQFP PTA4/KBI5/RX2/ADC2/LCD25 PTB2/LCD31 PTA5/KBI6/TPM2CH0/ADC3/LCD26 PTB1/LCD30 PTA6/KBI7/TPM2CH1/ADC4/LCD27 PTB0/LCD29 PTA7/TPMCLK/ADC5/LCD28 PTD1/LCD1 PTC5/BKGD/MS PTD0/LCD0 PTC6/RESET CAP1 PTH4/RX1/KBI2/TPM1CH1/ADC10 CAP2 PTH5/TX1/KBI3/TPM1CH0/ADC11 PTF3/SS/KBI0/TPM2CH5 Figure 2-2. 64-Pin LQFP NOTE are internally connected to V REFH REFL MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 30 PTD6/LCD6 PTD5/LCD5 PTA1/SCL/LCD22 PTA2/SDA/ADC0/LCD23 PTD4/LCD4 PTD3/LCD3 PTA3/KBI4/TX2/ADC1/LCD24 PTD2/LCD2 PTA4/KBI5/RX2/ADC2/LCD25 48-Pin LQFP PTD1/LCD1 PTA5/KBI6/TPM2CH0/ADC3/LCD26 PTD0/LCD0 PTA6/KBI7/TPM2CH1/ADC4/LCD27 PTA7/TPMCLK/ADC5/LCD28 CAP1 PTC5/BKGD/MS CAP2 PTC6/RESET PTF3/SS/KBI0/TPM2CH5 Figure 2-3. 48-Pin LQFP NOTE are internally connected to V REFH REFL MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 31: Recommended System Connections

    Chapter 2 Pins and Connections Recommended System Connections Figure 2-4 shows pin connections that are common to MC9S08LG32 series application systems. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 32 When PTC6 is configured as RESET, pin becomes bi-directional with output being open-drain drive containing an internal pullup device. When PTC5 is configured as BKGD, pin becomes bi-directional. LCD mode shown is for Charge pump enabled, other configurations are necessary for different LCD modes. Figure 2-4. Basic System Connections MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 33: Power

    C and C (which are usually of the same size). As a first-order approximation, use 10 pF as an estimate of combined pin and PCB capacitance for each oscillator pin (EXTAL and XTAL). MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 34: Reset

    The BKGD/MS pin is used primarily with BDC communications, and features a custom protocol that uses 16 clock cycles of the target MCU’s BDC clock per bit time. The target MCU’s BDC clock can run as fast MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 35: Irq

    LCD Driver Pins The MC9S08LG32 series of MCUs provide 45 LCD driver pins for the 80-pin packages, 37 pins for the 64-pin packages, and 29 pins for the 48-pin packages. Each LCD pin has pin enable control, so you can choose to use any LCD pin as either LCD driver or GPIO.

  • Page 36: General-Purpose I/O (Gpio) And Peripheral Ports

    2.3.7 General-Purpose I/O (GPIO) and Peripheral Ports The MC9S08LG32 series of MCUs support up to 69 GPIO pins including 2 output-only pins that are shared with on-chip peripheral functions (timers, serial I/O, LCD, ADC, etc.). The GPIO output-only pins (PTC5/BKGD/MS and PTC6/RESET) are bi-directional when configured as BKGD and RESET, respectively.
  • Page 37 — — PTF6 XTAL — — — — — — REFH — — — REFL — PTH6 TPM2CH5 KBI0 ADC15 — PTF2 SPSCK TPM1CH1 ADC14 PTF1 TPM1CH0 ADC13 — PTF0 KBI3 TPM2CH2 ADC12 MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 38 — — PTG1 LCD34 — — — — PTG0 LCD33 — — — PTE5 LCD13 — — — PTE4 LCD12 — — — PTE3 LCD11 — — — PTE2 LCD10 — — — MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 39 Table 2-1. Pin Availability by Package Pin-Count (continued) Packages <-- Lowest Priority --> Highest Port Pin Alt 1 Alt 2 Alt 3 Alt 4 PTE1 LCD9 — — — PTE0 LCD8 — — — MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 40 Chapter 2 Pins and Connections MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 41: Chapter 3 Modes Of Operation

    — Stop2 — Partial power down of internal circuits, RAM content is retained, and the I/O states are held. Run Mode This is the normal operating mode for the MC9S08LG32 series. In this mode, the CPU executes code from internal memory with execution beginning at the address fetched from memory at 0xFFFE–0xFFFF after reset.

  • Page 42: Wait Mode

    Active background mode is used to program a bootloader or user application program into the flash program memory before the MCU is operated in run mode for the first time. When the MC9S08LG32 series is shipped from the Freescale Semiconductor factory, the flash program memory is erased by default, unless specifically noted.

  • Page 43: Stop Modes

    The LCD driver pins continue to drive the signals necessary to display the LCD data. To exit from stop2 mode, assert the wakeup pins (PTC6/RESET or PTF2/IRQ) or through RTC interrupt or POR. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 44: Stop3 Mode

    If stop3 is exited by means of the RESET pin, the MCU is reset and operation resumes after taking the reset vector. Using an internal interrupt sources to exit, results in the MCU taking an appropriate interrupt vector. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 45: Active Bdm Enabled In Stop Mode

    ICS in STOP. OSCOUT standby bit is set and STOP optionally on. instruction executed.) Note on—stop that stop3 is used in place of currents ICSLCLK still active. stop2 if the BDM or LVD is enabled. increased. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 46 Stop3 Standby Stop2 Partial powerdown Stop3 Stop2 Figure 3-1. Allowable Power Mode Transitions for the MC9S08LG32 Series Figure 3-1 illustrates mode state transitions allowed between the legal states shown in Table 3-1. Table 3-3 defines triggers for the various state transitions shown in Figure 3-1.
  • Page 47 Stop2 assert zero on wakup pins (PTC6/RESET or PTF2/IRQ) or RTC interrupt or POR An analog connection from these pins to the on-chip regulator wakes up the regulator, which initiates a power-on-reset sequence. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 48: On-Chip Peripheral Modules In Stop Modes

    If LVDSE is set when entering stop2, the MCU will actually enter stop3. Requires the LVD to be enabled, else in standby. See Section 3.6.4, “LVD Enabled in Stop Mode”. ERCLKEN and EREFSTEN set in ICSC2, else in standby. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 49: Chapter 4 Memory

    Chapter 4 Memory Introduction This chapter describes the on-chip memory in the MC9S08LG32 series of MCUs. It details the memory map, vector and bit assignments, registers and control bits, and other RAM and flash features. MC9S08LG32 Series Memory Map As shown in...

  • Page 50: Reset And Interrupt Vector Assignments

    Table 4-1 shows the address assignments for reset and interrupt vectors. The vector names shown in this table are labels used in the Freescale Semiconductor equate file for the MC9S08LG32 series. Table 4-1. Reset and Interrupt Vectors (Sheet 1 of 2)
  • Page 51 SCI1 Receive Vsci1rx 0xFFF0:0xFFF1 SCI1 Error Vsci1err 0xFFF2:0xFFF3 TPM1 Overflow Vtpm1ovf 0xFFF4:0xFFF5 TPM1 Channel 1 Vtpm1ch1 0xFFF6:0xFFF7 TPM1 Channel 0 Vtpm1ch0 0xFFF8:0xFFF9 Low Voltage Warning Vlvw 0xFFFA:0xFFFB Virq 0xFFFC:0xFFFD Vswi 0xFFFE:0xFFFF Reset Vreset MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 52: Register Addresses And Bit Assignments

    Chapter 4 Memory Register Addresses and Bit Assignments The register groups in the MC9S08LG32 series consist of the following locations in the memory map: • Direct-page registers are located at the first 96 locations. Access these locations with efficient direct addressing mode instructions.
  • Page 53 TPM2C0SC CH0F CH0IE MS0B MS0A ELS0B ELS0A 0x0026 TPM2C0VH Bit 15 Bit 8 0x0027 TPM2C0VL Bit 7 Bit 0 0x0028 TPM2C1SC CH1F CH1IE MS1B MS1A ELS1B ELS1A 0x0029 TPM2C1VH Bit 15 Bit 8 MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 54 ADCV5 ADCV4 ADCV3 ADCV2 ADCV1 ADCV0 0x0051 ADCCFG ADLPC ADIV ADLSMP MODE ADICLK 0x0052 APCTL1 ADPC7 ADPC6 ADPC5 ADPC4 ADPC3 ADPC2 ADPC1 ADPC0 0x0053 APCTL2 ADPC15 ADPC14 ADPC13 ADPC12 ADPC11 ADPC10 ADPC9 ADPC8 MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 55 BPCLCD5 BPBLCD5 BPALCD5 0x0836 LCDWF6 BPHLCD6 BPGLCD6 BPFLCD6 BPELCD6 BPDLCD6 BPCLCD6 BPBLCD6 BPALCD6 0x0837 LCDWF7 BPHLCD7 BPGLCD7 BPFLCD7 BPELCD7 BPDLCD7 BPCLCD7 BPBLCD7 BPALCD7 0x0838 LCDWF8 BPHLCD8 BPGLCD8 BPFLCD8 BPELCD8 BPDLCD8 BPCLCD8 BPBLCD8 BPALCD8 MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 56 LCDWF44 BPHLCD44 BPGLCD44 BPFLCD44 BPELCD44 BPDLCD44 BPCLCD44 BPBLCD44 BPALCD44 High-page registers, shown in Table 4-4, are accessed much less often than other I/O and control registers so they have been located outside the direct addressable memory space, starting at 0x1800. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 57 0x182F — — — — — — — — 0x1830 PINPS1 KBI7 KBI6 KBI5 KBI4 KBI3 KBI2 KBI1 KBI0 0x1831 PINPS2 TPM2[5] TPM2[4] TPM2[3] TPM2[2] TPM2[1] TPM2[0] TPM1[1] TPM1[0] 0x1832 PINPS3 MISO MOSI MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 58 PTGSE2 PTGSE1 PTGSE0 0x186A PTGDS PTGDS7 PTGDS6 PTGDS5 PTGDS4 PTGDS3 PTGDS2 PTGDS1 PTGDS0 0x186B Reserved — — — — — — — — 0x186C PTHPE PTHPE7 PTHPE6 PTHPE5 PTHPE4 PTHPE3 PTHPE2 PTHPE1 PTHPE0 MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 59: Reserved Flash Locations

    KEYEN bit to 0. If the security key is disabled, the only way to disengage security is by mass erasing the flash if needed (normally through the background MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 60: Ram

    For compatibility with M68HC05 MCUs, the HCS08 resets the stack pointer to 0x00FF. In the MC9S08LG32 series, it is usually best to reinitialize the stack pointer to the top of the RAM so the direct page RAM can be used for frequently accessed RAM variables and bit-addressable program variables.

  • Page 61: Features

    Features of the flash memory include: • Flash size — MC9S08LG32: 32,768 bytes (16,384 bytes in Flash A, 16,384 bytes in Flash B) — MC9S08LG16: 18,432 bytes (2,048 bytes in Flash A, 16,384 in Flash B) • Single power supply program and erase •...

  • Page 62: Program And Erase Command Execution

    This must be done only once following a reset. 4. Wait until the FCCF bit in FSTAT is set. As soon as FCCF= 1, the operation has completed successfully. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 63: Burst Program Execution

    A row of flash memory consists of 64 bytes. A byte within a row is selected by addresses A5 through A0. A new row begins when addresses A5 through A0 are all zero. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 64 Wait at least four bus cycles before TO LAUNCH COMMAND checking FCBEF or FCCF. AND CLEAR FCBEF FPVIO OR ERROR EXIT FACCERR? NEW BURST COMMAND? FCCF? DONE Figure 4-3. Flash Burst Program Flowchart MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 65: Access Errors

    This address is formed by concatenating FPS7:FPS1 with logic 1 bits as shown. For example, to protect the last 1536 bytes of memory (addresses 0xFA00 through 0xFFFF), the MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 66: Vector Redirection

    Security The MC9S08LG32 series includes circuitry to prevent unauthorized access to the contents of flash and RAM memory. When security is engaged, flash and RAM are considered secure resources. Direct-page registers, high-page registers, and the background debug controller are considered unsecured resources.

  • Page 67: Flash Registers And Control Bits

    Flash Registers and Control Bits The flash module has six 8-bit registers in the high-page register space. Two locations (NVOPT, NVPROT) in the nonvolatile register space in flash memory are copied into corresponding high-page MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 68: Flash Clock Divider Register (Fcdiv)

    PRDIV8 = 0 — f Eqn. 4-1 FCLK ÷ (8 × (DIV + 1)) if PRDIV8 = 1 — f Eqn. 4-2 FCLK Table 4-8 shows the appropriate values for PRDIV8 and DIV for selected bus frequencies. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 69: Flash Options Register (Fopt And Nvopt)

    SEC01:SEC00 changes to 1:0 after successful backdoor key entry or a successful blank check of flash. For more detailed information about security, refer to Section 4.7, “Security.” MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 70: Flash Configuration Register (Fcnfg)

    FPDIS Reset This register is loaded from nonvolatile location NVPROT during reset. Background commands can be used to change the contents of these bits in FPROT. Figure 4-8. Flash Protection Register (FPROT) MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 71: Flash Status Register (Fstat)

    (the erroneous command is ignored). FPVIOL is cleared by writing a 1 to FPVIOL. 0 No protection violation. 1 An attempt was made to erase or program a protected location. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 72: Flash Command Register (Fcmd)

    All other command codes are illegal and generate an access error. It is not necessary to perform a blank check command after a mass erase operation. Only blank check is required as part of the security unlocking mechanism. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 73: Chapter 5 Resets, Interrupts, And General System Control

    This section discusses basic reset and interrupt mechanisms and the various sources of reset and interrupt in the MC9S08LG32 series. Some interrupt sources from peripheral modules are discussed in greater detail in other sections of this document. This section gathers basic information about all reset and interrupt sources in one place for easy reference.

  • Page 74: Computer Operating Properly (Cop) Watchdog

    In background debug mode, the COP counter does not increment. When the bus clock source is selected, the COP counter does not increment while the system is in stop mode. The COP counter resumes as soon as the MCU exits stop mode. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 75: Interrupts

    RTI that is used to return from the ISR. If more than one interrupt is pending when the I bit is cleared, the highest priority source is serviced first (see Table 5-2). MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 76: Interrupt Stack Frame

    (IRQ) input. As an IRQ input, you can choose the polarity of edges or levels detected (IRQEDG), whether the pin detects edges-only or edges and levels (IRQMOD) and whether an event causes an interrupt or only sets the IRQF flag which can be polled by software (IRQIE). MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 77: Interrupt Vectors, Sources, And Local Masks

    CCR) is 0, the CPU finishes the current instruction; stack the PCL, PCH, X, A, and CCR CPU registers; set the I bit; and then fetch the interrupt vector for the highest priority pending interrupt. Processing then continues in the interrupt service routine. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 78 Vswi Core SWI Instruction — Software interrupt 0xFFFE/0xFFFF Vreset System COPE Watchdog timer control LVDRE Low-voltage detect RESET pin RSTPE External pin Illegal opcode — Illegal opcode Highest Illegal address — Illegal address MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 79: Low-Voltage Detect (Lvd) System

    Peripheral Clock Gating The MC9S08LG32 series includes a clock gating system to manage the bus clock sources to the individual peripherals. Using this system, you can enable or disable the bus clock to each of the peripherals at the clock source, eliminating unnecessary clocks to peripherals which are not in use and thereby reducing the overall run and wait mode currents.

  • Page 80: Reset, Interrupt, And System Control Registers And Control Bits

    When IRQEDG = 1 and the internal pull device is enabled, the pullup device is reconfigured as an optional pulldown device. 0 IRQ is falling edge or falling edge/low-level sensitive. 1 IRQ is rising edge or rising edge/high-level sensitive. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 81 Section 5.5.2.2, “Edge and Level Sensitivity,” for more details. 0 IRQ event on falling edges or rising edges only. 1 IRQ event on falling edges and low levels or on rising edges and high levels. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 82: System Reset Status Register (Srs)

    STOPE = 0 in the SOPT register. The BGND instruction is considered illegal if active background mode is disabled by ENBDM = 0 in the BDCSC register. 0 Reset not caused by an illegal opcode. 1 Reset caused by an illegal opcode. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 83: System Background Debug Force Reset Register (Sbdfr)

    PTC5/BKGD/MS must be high immediately after issuing WRITE_BYTE command. To enter BDM, PTC5/BKGD/MS must be low immediately after issuing WRITE_BYTE command. See the data sheet for more information. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 84: System Options Register 1 (Sopt1)

    GPIO. This pin defaults to its RESET function following an MCU POR or LVD. When RSTPE is set, an internal pullup device is enabled on RESET. 0 PTC6/RESET pin functions as PTC6. 1 PTC6/RESET pin functions as RESET. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 85: System Options Register 2 (Sopt2)

    Chapter 5 Resets, Interrupts, and General System Control 5.8.5 System Options Register 2 (SOPT2) This high-page register contains bits to configure MCU specific features on the MC9S08LG32 series devices. COPCLKS SPIFE Reset: = Unimplemented or Reserved Figure 5-6. System Options Register 2 (SOPT2) This bit can be written only one time after reset.

  • Page 86: System Device Identification Register (Sdidh, Sdidl)

    Bits 7:4 are reserved. Reading these bits result in an indeterminate value; writes have no effect. Reserved Part Identification Number — Each derivative in the HCS08 Family has a unique identification number. The ID[11:8] MC9S08LG32 is hard coded to the value 0x02A. See also ID bits in Table 5-9. Reset: = Unimplemented or Reserved Figure 5-8.

  • Page 87: System Power Management Status And Control 1 Register (Spmsc1)

    Provided LVDE = 1, this read/write bit determines whether the low-voltage detect function operates when the MCU is in stop mode. This bit has no effect if the LVDE bit is a logic 0. 0 Low-Voltage detect disabled during stop mode. 1 Low-Voltage detect enabled during stop mode. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 88: System Power Management Status And Control 2 Register (Spmsc2)

    Partial Power Down Flag PPDF This read-only status bit indicates that the MCU has recovered from stop2 mode. 0 MCU has not recovered from stop2 mode. 1 MCU recovered from stop2 mode. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 89 {LVDV,LVWV} = 11) 4.50 4.70 SUPPLY LVWXHH Low LVW trip point (V rising, {LVDV,LVWV} = 11) 4.60 4.80 SUPPLY All values measured with respect to V SUPPLY All values with factory trim MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 90: System Clock Gating Control 1Register (Scgc1)

    SCI1 Clock Gate Control — This bit controls the clock gate to the SCI1 module. SCI1 0 Bus clock to the SCI1 module is disabled. 1 Bus clock to the SCI1 module is enabled. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 91: System Clock Gating Control 2 Register (Scgc2)

    SPI Clock Gate Control — This bit controls the clock gate to the SPI module. 0 Bus clock to the SPI module is disabled. 1 Bus clock to the SPI module is enabled. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 92: Pin Position Control Register (Pinps1)

    0 KBI1 sourced from PTF4 1 KBI1 sourced from PTH7 KBI0 Pin Position — This bit controls the pin position of KBI0. KBI0 0 KBI0 sourced from PTF3 1 KBI0 sourced from PTH6 MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 93: Pin Position Control Register (Pinps2)

    0 TPM1[1] sourced from PTF2 1 TPM1[1] sourced from PTH4 TPM1[0] Pin Position — This bit controls the pin position of TPM1[0]. TPM1[0] 0 TPM1[0] sourced from PTF1 1 TPM1[0] sourced from PTH5 MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 94: Pin Position Control Register (Pinps3)

    SCK Pin Position — This bit controls the pin position of SCK. 0 SCK sourced from PTF2. 1 SCK sourced from PTI4. SS Pin Position — This bit controls the pin position of SS. 0 SS sourced from PTF3. 1 SS sourced from PTI5. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 95: Pin Position Control Register (Pinps4)

    TX1 Pin Position — This bit controls the pin position of TX1. 0 TX1 sourced from PTF0. 1 TX1 sourced from PTH5. RX1 Pin Position — This bit controls the pin position of RX1. 0 RX1 sourced from PTF1. 1 RX1 sourced from PTH4. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 96 Chapter 5 Resets, Interrupts, and General System Control MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 97: Chapter 6 Parallel Input/Output Control

    Parallel Input/Output Control Introduction This section explains software controls related to parallel input/output (I/O) and pin control. The MC9S08LG32 has nine parallel I/O ports (PTA-PTI) which include a total of 69 I/O pins, including two output-only pins. See Chapter 2, “Pins and Connections,”...

  • Page 98: Pullup, Slew Rate, And Drive Strength

    GPIO that are muxed with LCD pins, the internal pullup is not disabled when in open drain, output mode. Similarly the internal pullup for GPIO muxed with open drain RESET pin is not disabled in the output mode. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 99: Port Slew Rate Enable

    • If the LCD module is configured to operate in Stop modes, the drive mode of the GPIO shared with LCD is retained upon stop recovery. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 100: Parallel I/O And Pin Control Registers

    6.7.1 Port A Registers Port A is controlled by the registers listed below. All the pins of port A are shared with LCD. These pins have special behavior as explained in Section 6.2. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 101 Data Direction for Port A Bits — These read/write bits control the direction of port A pins and what is read for PTADD[7:0] PTAD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port A bit n and PTAD reads return the contents of PTADn. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 102 PTA pin. For port A pins that are configured as inputs, these bits have no effect. 0 Output slew rate control disabled for port A bit n. 1 Output slew rate control enabled for port A bit n. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 103 PTA pin. For port A pins that are configured as inputs, these bits have no effect. 0 Low output drive strength selected for port A bit n. 1 High output drive strength selected for port A bit n. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 104: Port B Registers

    Data Direction for Port B Bits — These read/write bits control the direction of Port B pins and what is read for PTBDD[7:0] PTBD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for Port B bit n and PTBD reads return the contents of PTBDn. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 105 PTB pin. For Port B pins that are configured as inputs, these bits have no effect. 0 Output slew rate control disabled for Port B bit n. 1 Output slew rate control enabled for Port B bit n. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 106 PTB pin. For Port B pins that are configured as inputs, these bits have no effect. 0 Low output drive strength selected for Port B bit n. 1 High output drive strength selected for Port B bit n. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 107: Port C Registers

    Data Direction for Port C Bits — These read/write bits control the direction of Port C pins and what is read for PTCDD[6:0] PTCD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for Port C bit n and PTCD reads return the contents of PTCDn. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 108 PTC pin. For Port C pins that are configured as inputs, these bits have no effect. 0 Output slew rate control disabled for Port C bit n. 1 Output slew rate control enabled for Port C bit n. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 109 PTC pin. For Port C pins that are configured as inputs, these bits have no effect. 0 Low output drive strength selected for Port C bit n. 1 High output drive strength selected for Port C bit n. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 110: Port D Registers

    Data Direction for Port D Bits — These read/write bits control the direction of Port D pins and what is read for PTDDD[7:0] PTDD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for Port D bit n and PTDD reads return the contents of PTDDn. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 111 PTD pin. For Port D pins that are configured as inputs, these bits have no effect. 0 Output slew rate control disabled for Port D bit n. 1 Output slew rate control enabled for Port D bit n. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 112 PTD pin. For Port D pins that are configured as inputs, these bits have no effect. 0 Low output drive strength selected for Port D bit n. 1 High output drive strength selected for Port D bit n. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 113: Port E Registers

    Data Direction for Port E Bits — These read/write bits control the direction of Port E pins and what is read for PTEDD[7:0] PTED reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for Port E bit n and PTED reads return the contents of PTEDn. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 114 PTE pin. For Port E pins that are configured as inputs, these bits have no effect. 0 Output slew rate control disabled for Port E bit n. 1 Output slew rate control enabled for Port E bit n. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 115 PTE pin. For Port E pins that are configured as inputs, these bits have no effect. 0 Low output drive strength selected for Port E bit n. 1 High output drive strength selected for Port E bit n. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 116: Port F Registers

    Data Direction for Port F Bits — These read/write bits control the direction of Port F pins and what is read for PTFDD[7:0] PTFD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for Port F bit n and PTFD reads return the contents of PTFDn. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 117 PTF pin. For Port F pins that are configured as inputs, these bits have no effect. 0 Output slew rate control disabled for Port F bit n. 1 Output slew rate control enabled for Port F bit n. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 118 PTF pin. For Port F pins that are configured as inputs, these bits have no effect. 0 Low output drive strength selected for Port F bit n. 1 High output drive strength selected for Port F bit n. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 119: Port G Registers

    Data Direction for Port G Bits — These read/write bits control the direction of Port G pins and what is read for PTGDD[7:0] PTGD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for Port G bit n and PTGD reads return the contents of PTGDn. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 120 PTG pin. For Port G pins that are configured as inputs, these bits have no effect. 0 Output slew rate control disabled for Port G bit n. 1 Output slew rate control enabled for Port G bit n. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 121 PTG pin. For Port G pins that are configured as inputs, these bits have no effect. 0 Low output drive strength selected for Port G bit n. 1 High output drive strength selected for Port G bit n. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 122: Port H Registers

    Data Direction for Port H Bits — These read/write bits control the direction of Port H pins and what is read for PTHDD[7:0] PTHD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for Port H bit n and PTHD reads return the contents of PTHDn. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 123 PTH pin. For Port H pins that are configured as inputs, these bits have no effect. 0 Output slew rate control disabled for Port H bit n. 1 Output slew rate control enabled for Port H bit n. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 124 PTH pin. For Port H pins that are configured as inputs, these bits have no effect. 0 Low output drive strength selected for Port H bit n. 1 High output drive strength selected for Port H bit n. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 125: Port I Registers

    Data Direction for Port I Bits — These read/write bits control the direction of Port I pins and what is read for PTIDD[5:0] PTID reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for Port I bit n and PTID reads return the contents of PTIDn. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 126 PTI pin. For Port I pins that are configured as inputs, these bits have no effect. 0 Output slew rate control disabled for Port I bit n. 1 Output slew rate control enabled for Port I bit n. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 127 PTI pin. For Port I pins that are configured as inputs, these bits have no effect. 0 Low output drive strength selected for Port I bit n. 1 High output drive strength selected for Port I bit n. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 128: Chapter 7 Keyboard Interrupt (S08Kbiv2)

    To conserve power, this bit can be cleared to disable the clock to this module when not in use. For more details, see Section 5.7, “Peripheral Clock Gating.” MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 129 RX2/PTI0 VOLTAGE REGULATOR Available only on 80-pin package Available only on 64-pin and 80-pin package */Default function out of reset/* REFH REFL Figure 7-1. MC9S08LG32 Series Block Diagram Highlighting KBI Block and Pins MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 130: Features

    KBI in Active Background Mode When the microcontroller is in active background mode, the KBI will continue to operate normally. 7.1.5 Block Diagram The block diagram for the keyboard interrupt module is shown Figure 7-2. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 131: External Signal Description

    Some MCUs may have more than one KBI, so register names include placeholder characters to identify which KBI is being referenced. 7.3.1 KBI Status and Control Register ( KBISC contains the status flag and control bits, which are used to configure the KBI. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 132: Kbi Pin Enable Register (Kbipe)

    Keyboard Pin Enables — Each of the KBIPEn bits enable the corresponding keyboard interrupt pin. KBIPEn 0 Pin not enabled as keyboard interrupt. 1 Pin enabled as keyboard interrupt. 7.3.3 KBI Edge Select Register (KBIES) KBIES contains the edge select control bits. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 133: Functional Description

    CPU. Clearing of KBF is accomplished by writing a 1 to KBACK in KBISC provided all enabled keyboard inputs are at their deasserted levels. KBF will remain set if any enabled KBI pin is asserted while attempting to clear by writing a 1 to KBACK. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 134: Kbi Pullup/Pulldown Resistors

    3. If using internal pullup/pulldown device, configure the associated pullup enable bits in PTxPE. 4. Enable the KBI pins by setting the appropriate KBIPEn bits in KBIPE. 5. Write to KBACK in KBISC to clear any false interrupts. 6. Set KBIE in KBISC to enable interrupts. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 135: Chapter 8 Central Processor Unit (S08Cpuv5)

    (BCD) operations • Efficient bit manipulation instructions • Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions • Stop and Wait instructions to invoke low-power operating modes MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 136: Programmer's Model And Cpu Registers

    A or transferred to A where arithmetic and logical operations can then be performed. For compatibility with the earlier M68HC05 Family, H is forced to 0x00 during reset. Reset has no effect on the contents of X. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 137: Stack Pointer (Sp)

    For a more detailed explanation of how each instruction sets the CCR bits, refer to the HCS08 Family Reference Manual, volume 1, Freescale Semiconductor document order number HCS08RMv1. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 138 7 of the accumulator or when a subtraction operation requires a borrow. Some instructions — such as bit test and branch, shift, and rotate — also clear or set the carry/borrow flag. 0 No carry out of bit 7 1 Carry out of bit 7 MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 139: Addressing Modes

    16-bit address where the desired operand is located. This is faster and more memory efficient than specifying a complete 16-bit address for the operand. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 140: Extended Addressing Mode (Ext)

    This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus an unsigned 8-bit offset included in the instruction as the address of the operand needed to complete the instruction. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 141: Special Operations

    After the CCR contents are pushed onto the stack, the I bit in the CCR is set to prevent other interrupts while in the interrupt service routine. Although it is possible to clear the I bit with an instruction in the MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 142: Wait Mode Operation

    MCU even if it is in stop mode. Recovery from stop mode depends on the particular HCS08 and whether the oscillator was stopped in stop mode. Refer to Chapter 3, “Modes of Operation,” for more details. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 143: Bgnd Instruction

    Software-based breakpoints can be set by replacing an opcode at the desired breakpoint address with the BGND opcode. When the program reaches this breakpoint address, the CPU is forced to active background mode rather than continuing the user program. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 144: Hcs08 Instruction Set Summary

    H = Half carry, bit 4 I = Interrupt mask, bit 3 N = Negative indicator, bit 2 Z = Zero indicator, bit 1 C = Carry/borrow, bit 0 (carry out of bit 7) MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 145 The assembler will calculate the 8-bit signed offset and include it in the object code for this instruction. Address modes INH = Inherent (no operands) MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 146 Logical AND ee ff prpp – Þ Þ – 0 1 1 – A ← (A) & (M) AND oprx8,X AND ,X AND oprx16,SP 9E D4 ee ff pprpp AND oprx8,SP 9E E4 prpp MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 147 Branch if IRQ Pin High (if IRQ pin = 1) – 1 1 – – – – – 2F rr BIL rel Branch if IRQ Pin Low (if IRQ pin = 0) – 1 1 – – – – – 2E rr MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 148 DIR (b3) rfwpp Set Bit n in Memory (Mn ← 1) BSET n,opr8a – 1 1 – – – – – DIR (b4) rfwpp DIR (b5) rfwpp DIR (b6) rfwpp DIR (b7) rfwpp MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 149 Memory CPHX #opr16i jj kk Þ 1 1 – – Þ Þ Þ (H:X) – (M:M + $0001) CPHX opr8a rrfpp (CCR Updated But Operands Not CPHX oprx8,SP 9E F3 prrfpp Changed) MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 150 Push (PCL); SP ← (SP) – $0001 JSR oprx16,X – 1 1 – – – – – ee ff pssppp Push (PCH); SP ← (SP) – $0001 JSR oprx8,X ssppp PC ← Unconditional Address JSR ,X ssppp MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 151 In IX+/DIR and DIR/IX+ Modes, IMM/DIR ii dd pwpp H:X ← (H:X) + $0001 MOV ,X+,opr8a IX+/DIR rfwpp Unsigned multiply – 1 1 0 – – – 0 ffffp X:A ← (X) × (A) MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 152 ROL oprx8,SP 9E 69 prfwpp ROR opr8a rfwpp Rotate Right through Carry RORA RORX Þ 1 1 – – Þ Þ Þ ROR oprx8,X rfwpp ROR ,X rfwp ROR oprx8,SP 9E 66 prfwpp MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 153 Store X (Low 8 Bits of Index Register) ee ff pwpp – Þ Þ – STX oprx8,X in Memory 0 1 1 – M ← (X) STX ,X STX oprx16,SP 9E DF ee ff ppwpp oprx8,SP 9E EF pwpp MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 154 Transfer SP to Index Reg. – 1 1 – – – – – H:X ← (SP) + $0001 Transfer X (Index Reg. Low) to Accumulator – 1 1 – – – – – A ← (X) MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 155 – 1 1 – – – – – SP ← (H:X) – $0001 Enable Interrupts; Wait for Interrupt WAIT – 1 1 – 0 – – – fp... I bit ← 0; Halt CPU MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 156 DIR to DIR IMM to DIR IX1+ Indexed, 1-Byte Offset with IX+D IX+ to DIR DIX+ DIR to IX+ Post Increment Opcode in HCS08 Cycles Hexadecimal Instruction Mnemonic Addressing Mode Number of Bytes MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 157 DIR to IX+ Post Increment Note: All Sheet 2 Opcodes are Preceded by the Page 2 Prebyte (9E) Prebyte (9E) and Opcode in 9E60 HCS08 Cycles Hexadecimal Instruction Mnemonic Addressing Mode Number of Bytes MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 158: Chapter 9 Lcd Module (S08Lcdlpv1)

    LL3_2 2. For MC9S08LG32 series MCUs, the devices working at –40 °C to 85 °C temperature range have the change pump feature only, whereas devices working at –40 °C to 105 °C do not have this feature. For higher temperatures (–40 °C to 105 °C) register bias in high gain mode is recommended.
  • Page 159 REGULATOR Available only on 80 pin package Available only on 64 and 80 pin package REFH */Default function out of reset/* REFL Figure 9-1. MC9S08LG32 Series Block Diagram Highlighting LCD Block and Pins MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 160: Features

    Backplane reassignment to assist in vertical scrolling on dot-matrix displays • Software configurable LCD frame frequency interrupt • Internal ADC channels are connected to V to monitor their magnitudes. This feature allows software to adjust the contrast. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 161: Modes Of Operation

    Stop2 provides the lowest power consumption state where the LCD module is functional. To operate the LCD in stop2 mode, use an external crystal. 9.1.7 Block Diagram Figure 9-2 is a block diagram of the LCD module. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 162: External Signal Description

    Switchable frontplane/backplane driver that connects directly to the display LCD[44:0] can operate as GPIO pins — LCD bias voltages LCD bias voltages LL3, LL3_2 LCD charge pump capacitance V — Charge pump capacitor pins cap1 cap2 MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 163: Lcd[44:0]

    LCLK1 LCLK0 DUTY2 DUTY1 DUTY0 Reset = Unimplemented or Reserved Figure 9-3. LCD Control Register 0 (LCDC0) Read: anytime Write: LCDEN anytime. Do not change SOURCE, LCLCK, or DUTY while LCDEN = 1. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 164: Lcd Control Register 1 (Lcdc1)

    111 Use 8 BP (1/8 duty cycle). 9.3.2 LCD Control Register 1 (LCDC1) LCDIEN FCDEN LCDWAI LCDSTP Reset = Unimplemented or Reserved Figure 9-4. LCD Control Register 1 (LCDC1) Read: anytime Write: anytime MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 165: Lcd Voltage Supply Register (Lcdsupply)

    Figure 9-5. LCD Voltage Supply Register (LCDSUPPLY) Read: anytime Write: anytime. For proper operation, do not modify VSUPPLY[1:0] while the LCDEN bit is asserted. VSUPPLY[1:0] must also be configured according to the external hardware power supply configuration. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 166: Lcd Regulated Voltage Control Register (Lcdrvc)

    10 - High Load (LCD glass capacitance 8000pf or lower) 11 - High Load (LCD glass capacitance 8000pf or lower) Op Amp Control — This feature is not available for MC9S08LG32 series. Writing to this bit is not recommended. BBYPASS Voltage Supply Control —...

  • Page 167: Lcd Blink Control Register (Lcdbctl)

    Equation 9-2 provides an expression for the LCD module blink rate Eqn. 9-2 LCDCLK LCD module blink rate (12+ BRATE[2:0]) LCD module blink rate calculations are provided in Section 9.4.3.2, “Blink Frequency.” MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 168: Lcd Status Register (Lcds)

    These registers should only be written with instructions that perform byte writes, using instructions that perform word writes will lead to invalid data being placed in the register. Initialize these registers before enabling the LCD module. Exiting stop2 mode does not require reinitializing the LCDPEN registers. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 169: Backplane Enable Registers 0-5 (Bpen0-Bpen5)

    LCD module. Exiting stop2 mode does not require reinitializing the LCDBPEN registers. These registers should only be written with instructions that perform byte writes, using instructions that perform word writes will lead to invalid data being placed in the register. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 170: Lcd Waveform Registers (Lcdwf[44:0])

    For an LCD pin configured as a backplane, the LCDWF registers controls the phase (A-H) in which the associated backplane pin is active. After reset, the LCDWF contents are indeterminate as indicated by Figure 9-11. Exiting stop2 mode does not require reinitializing the LCDWF registers. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 171 Indeterminate after reset LCDWF11 BPHLCD11 BPGLCD11 BPFLCD11 BPELCD11 BPDLCD11 BPCLCD11 BPBLCD11 BPALCD11 Reset Indeterminate after reset LCDWF12 BPHLCD12 BPGLCD12 BPFLCD12 BPELCD12 BPDLCD12 BPCLCD12 BPBLCD12 BPALCD12 Reset Indeterminate after reset Figure 9-11. LCD Waveform Registers (LCDWF[44:0]) MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 172 Reset Indeterminate after reset LCDWF25 BPHLCD25 BPGLCD25 BPFLCD25 BPELCD25 BPDLCD25 BPCLCD25 BPBLCD25 BPALCD25 Reset Indeterminate after reset LCDWF26 BPHLCD26 BPGLCD26 BPFLCD26 BPELCD26 BPDLCD26 BPCLCD26 BPBLCD26 BPALCD26 Figure 9-11. LCD Waveform Registers (LCDWF[44:0]) (continued) MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 173 LCDWF38 BPHLCD38 BPGLCD38 BPFLCD38 BPELCD38 BPDLCD38 BPCLCD38 BPBLCD38 BPALCD38 Reset Indeterminate after reset LCDWF39 BPHLCD39 BPGLCD39 BPFLCD39 BPELCD39 BPDLCD39 BPCLCD39 BPBLCD39 BPALCD39 Reset Indeterminate after reset Figure 9-11. LCD Waveform Registers (LCDWF[44:0]) (continued) MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 174: Functional Description

    Out of reset, the LCD module is configured with default settings, but these settings are not optimal for every application. The LCD module provides several versatile configuration settings and options to support varied implementation requirements, including: • Frame frequency MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 175: Lcd Driver Description

    LCD panel, but because each frontplane driver can drive only one LCD segment, static driving limits the LCD segments that can be driven with a given number of frontplane pins. In static mode, only one backplane is required. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 176 LCD clock tree. The clock tree shows the two possible clock sources and the LCD frame frequency and blink frequency clock source. The LCD blink frequency is discussed in Section 9.4.3.2, “Blink Frequency.” MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 177 The number of backplane phases is selected using the DUTY[2:0] bits. The LCD module base clock is used by the backplane sequencer to generate the LCD waveform data for the enabled phases (A-H). MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 178 This section shows the timing examples of the LCD output waveforms for the several modes of operation. As shown in Table 9-14, all examples use 1/3 bias mode. Table 9-14. Configurations for Example LCD Waveforms Bias Mode DUTY[2:0] Duty Cycle Example 1 Example 2 Example 3 MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 179 LCD[1] assigned to Phase B: LCDWF1 = 0x02 1 Frame Phase Phase Phase Phase Base_Clk Frame Interrupt LCD[0]/BP0 LCD[1]/BP1 LCDWF[n]= 0x02 = 00000010 BP0-FPn (OFF) BP1-FPn (ON) Figure 9-13. 1/2 Duty and 1/3 Bias (Low-Power Waveform) MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 180 LCD[3] assigned to Phase D: LCDWF3 = 0x08 1 Frame Phase Phase Base_Clk Frame Interrupt LCD[0]/BP0 LCD[1]/BP1 LCD[2]/BP2 LCD[3]/BP3 LCDWFn(0x09) =00001001 BP0–FPn (ON) BP1–FPn (OFF) Figure 9-14. 1/4 Duty and 1/3 Bias (Low-Power Waveform) MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 181 LCD[3] assigned to Phase D: LCDWF3 = 0x08 LCD[4] assigned to Phase E: LCDWF4 = 0x10 LCD[5] assigned to Phase F: LCDWF5 = 0x20 LCD[6] assigned to Phase G: LCDWF6 = 0x40 LCD[7] assigned to Phase H: LCDWF7 = 0x80 MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 182 Chapter 8 LCD Module (S08LCDLPV1) 1 Frame Phase Phase Base_Clk LCD[0]/BP0 LCD[1]/BP1 LCD[2]/BP2 LCD[3]/BP3 LCD[4]/BP4 LCD[5]/BP5 LCD[6]/BP6 LCD[7]/BP7 LCDWFn(0x69) BP0–FPn (ON) BP1–FPn (OFF) Figure 9-15. 1/8 Duty and 1/3 Bias (Low-power Waveform) MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 183: Lcdwf Registers

    Using the alternate display function an inverse display can be accomplished for x4 mode and less by placing inverse data in the alternate phases of the LCDWF registers. Table 9-15. Alternate Display Backplane Sequence Duty Backplane Sequence Alt. Backplane Sequence MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 184 LCD clock (LCDCLK) divided by the factor selected by the BRATE[2:0] bits. Table 9-17 shows LCD module blink frequency calculations for all values of BRATE[2:0] at a few common LCDCLK selections. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 185: Lcd Charge Pump, Voltage Divider, And Power Supply Operation

    V pins. LL3_2 Upon Reset the VSUPPLY[1:0] bits are configured to connect V to V . This configuration should be changed to match the application requirements before the LCD module is enabled. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 186 Using the voltage divider and charge pump, the LCD module can be used to generate various voltages. This LCD module configurability makes the LCD module compatible with both 3 V or 5 V LCD glass. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 187 V is driven externally for 5 V LCD Glass For 5 V glass operation V must equal 5 V. operation. must equal V Charge pump is used to generate V and V MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 188: Resets

    = 3.33 V • V = 3 V • V = 5 V 9.4.5 Resets During a reset, the LCD module system is configured in the default mode. The default mode includes the following settings: MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 189: Interrupts

    Configure LCD duty cycle (DUTY[2:0]). b) Select and configure LCD frame frequency (LCLK[2:0]). 5. LCDBCTL register a) Configure display mode (ALT and BLANK bits). b) Configure blink mode (BMODE). c) Configure blink frequency (BRATE[2:0]). MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 190: Initialization Examples

    Table 9-22. LCD Setup Requirements for Example 1 Operating LCD Glass Required Behavior in LCD Clock Blinking LCD Power Example Voltage, Operating Frame STOP and Source Mode/Rate Input Voltage segments Rate WAIT modes MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 191 LCD[0] to be active in Phase A, LCD[1] to be active in Phase LCDWF2 00000100 B...etc LCDWF3 00001000 LCDWF4 00010000 Note: Any backplane pin can be active in any phase. LCDWF5 00100000 LCDWF6 01000000 LCDWF7 10000000 MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 192 Blank bit is configured during LCD operation BMODE Blink Alternate = 1 BRATE[2:0] Select.5 Hz blink frequency using Table 9-17 LCDPEN[5:0] LCDPEN0 11111111 29 LCD pins need to be enabled. LCDPEN1 11111111 LCDPEN2 11111111 LCDPEN3 00011111 MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 193 Selects OSCOUT as the LCD clock source (32.768 kHz crystal) LCLK[2:0] For 1/8 duty cycle, select closest value to the desired 30 Hz LCD frame frequency (see Table 9-12) DUTY[2:0] For 168 segments (8x21), select 1/8 duty cycle MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 194: Application Information

    LCD module. The programmer’s model groups the LCD module register bit and bit field into functional groups. The model is a high-level illustration of the LCD module showing the module’s functional hierarchy including initialization and runtime control. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 195: Lcd Seven Segment Example Description

    A description of the connection between the LCD module and a seven segment LCD character is illustrated below to provide a basic example for a 1/3 duty cycle LCD implementation. The example uses three backplane pins (LCD[3], LCD[4] and LCD[5] and 3 frontplane pins (LCD[0], LCD[1], and LCD[2]). MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 196 – – – – – – To display the character “4”: LCDWF0 = XXXXX01X, LCDWF1 = XXXXX010, LCDWF2 =XXXXXX11 LCDWF0 LCDWF1 LCDWF2 X = don’t care Figure 9-18. Waveform Output from LCDWF Registers MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 197 Chapter 8 LCD Module (S08LCDLPV1) 9.6.1.1 LCD Module Waveforms DUTY = 1/3 1FRAME LCD3/BP0 LCD4/BP1 LCD5/BP2 BPALCD0 BPCLCD0 BPBLCD0 LCD0/FP0 — BPCLCD1 BPBLCD1 BPALCD1 LCD1/FP1 — BPCLCD2 BPBLCD2 BPALCD2 LCD2/FP2 — Figure 9-19. LCD Waveforms MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 198: Lcd Contrast Control

    Increasing the value of the LCD voltage will cause the energized segments on the LCD glass to become more opaque. Decreasing the value of the LCD voltage makes the energized segments on the LCD glass more transparent. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 199: Stop Mode Recovery

    When the MCU recovers from stop2 mode a reset sequence is initiated. All Control Registers should be re-written before the stop2 recovery acknowledge bit is set. The Registers LCDBPEN, LCDPEN and the LCDWF retain their values upon stop2 recovery and do not need to be re-written. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 200: Chapter 10 Analog-To-Digital Converter (S08Adc12V1)

    Introduction The 12-bit analog-to-digital converter (ADC) is a successive approximation ADC designed for operation within an integrated microcontroller system-on-chip. Figure 10-1 shows the MC9S08LG32 series with the ADC module highlighted. 10.1.1 ADC shared with LCD PTA2/SDA/ADC0/LCD23, PTA3/KBI4/TX2/ADC1/LCD24, PTA4/KBI5/RX2/ADC2/LCD25, PTA5/KBI6/TPM2CH0/ADC3/LCD26, PTA6/KBI7/TPM2CH1/ADC4/LCD27 and PTA7/TPMCLK/ADC5/LCD28 share ADC functionality with LCD pins.

  • Page 201: Module Configurations

    */Default function out of reset/* REFH REFL Figure 10-1. MC9S08LG32 Series Block Diagram Highlighting ADC Block and Pins 10.1.4 Module Configurations This section provides device-specific information for configuring the ADC on MC9S08LG32 series. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 202 The ADC, if enabled in stop3 mode, must be configured to use the asynchronous clock source, ADACK, to meet the ADC minimum frequency requirements. 10.1.4.2 Channel Assignments The ADC channel assignments for the MC9S08LG32 series devices are shown in Table 10-1. Reserved channels convert to an unknown value.
  • Page 203 Chapter 10 Analog-to-Digital Converter (S08ADC12V1) ALTCLK on the MC9S08LG32 series is connected to the ICSERCLK. See Chapter 11, “Internal Clock Source (S08ICSV3),” for more information. 10.1.4.4 Hardware Trigger The RTC can be enabled as a hardware trigger for the ADC module by setting the ADTRG bit in the ADCSC2 register.

  • Page 204: Features

    Selectable asynchronous hardware conversion trigger • Automatic compare with interrupt for less-than, or greater-than or equal-to, programmable value • Temperature sensor 10.1.6 ADC Module Block Diagram Figure 10-2 provides a block diagram of the ADC module MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 205: External Signal Description

    The ADC module supports up to 28 separate analog inputs. It also requires four supply/reference/ground connections. Table 10-2. Signal Properties Name Function AD27–AD0 Analog Channel inputs High reference voltage REFH Low reference voltage REFL Analog power supply Analog ground MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 206: Analog Power

    This section describes the function of the ADC status and control register (ADCSC1). Writing ADCSC1 aborts the current conversion and initiates a new conversion (if the ADCH bits are equal to a value other than all 1s). MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 207 Table 10-4. Input Channel Select ADCH Input Select 00000–01111 AD0–15 10000–11011 AD16–27 11100 Reserved 11101 REFH 11110 REFL 11111 Module disabled MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 208: Status And Control Register 2 (Adcsc2)

    ADCRH prevents the ADC from transferring subsequent conversion results into the result registers until ADCRL is read. If ADCRL is not read until after the next conversion is completed, the intermediate conversion result is lost. In 8-bit mode, there is no interlocking with ADCRL. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 209: Data Result Low Register (Adcrl)

    12-bit mode. ADCV11 ADCV10 ADCV9 ADCV8 Reset: Figure 10-7. Compare Value High Register (ADCCVH) MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 210: Compare Value Low Register (Adccvl)

    Longer sample times can also be used to lower overall power consumption when continuous conversions are enabled if high conversion rates are not required. 0 Short sample time 1 Long sample time MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 211: Pin Control 1 Register (Apctl1)

    The pin control registers disable the I/O port control of MCU pins used as analog inputs. APCTL1 is used to control the pins associated with channels 0–7 of the ADC module. ADPC7 ADPC6 ADPC5 ADPC4 ADPC3 ADPC2 ADPC1 ADPC0 Reset: Figure 10-10. Pin Control 1 Register (APCTL1) MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 212: Pin Control 2 Register (Apctl2)

    1 AD0 pin I/O control disabled 10.3.9 Pin Control 2 Register (APCTL2) APCTL2 controls channels 8–15 of the ADC module. ADPC15 ADPC14 ADPC13 ADPC12 ADPC11 ADPC10 ADPC9 ADPC8 Reset: Figure 10-11. Pin Control 2 Register (APCTL2) MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 213: 10Pin Control 3 Register (Apctl3)

    1 AD8 pin I/O control disabled 10.3.10 Pin Control 3 Register (APCTL3) APCTL3 controls channels 16–23 of the ADC module. ADPC23 ADPC22 ADPC21 ADPC20 ADPC19 ADPC18 ADPC17 ADPC16 Reset: Figure 10-12. Pin Control 3 Register (APCTL3) MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 214: Functional Description

    The ADC module has the capability of automatically comparing the result of a conversion with the contents of its compare registers. The compare function is enabled by setting the ACFE bit and operates with any of the conversion modes and configurations. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 215: Clock Select And Divide Control

    Conversions can be performed in 12-bit mode, 10-bit mode, or 8-bit mode as determined by the MODE bits. Conversions can be initiated by a software or hardware trigger. In addition, the ADC module can be MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 216 A write to ADCSC2, ADCCFG, ADCCVH, or ADCCVL occurs. This indicates a mode of operation change has occurred and the current conversion is therefore invalid. • The MCU is reset. • The MCU enters stop mode with ADACK not enabled. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 217 Single or first continuous 10-bit or 12-bit Subsequent continuous 8-bit; 17 ADCK cycles > f ADCK Subsequent continuous 10-bit or 12-bit; 20 ADCK cycles > f ADCK Subsequent continuous 8-bit; 37 ADCK cycles > f ADCK MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 218: Automatic Compare Function

    The bus clock, bus clock divided by two, and ADACK are available as conversion clock sources while in wait mode. The use of ALTCLK as the conversion clock source in wait is dependent on the definition of MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 219: Mcu Stop3 Mode Operation

    The ADC module is automatically disabled when the MCU enters stop2 mode. All module registers contain their reset values following exit from stop2. Therefore, the module must be re-enabled and re-configured following exit from stop2. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 220: Initialization Information

    Software trigger selected Bit 5 ACFE Compare function disabled Bit 4 ACFGT Not used in this example Bit 3:2 Reserved, always reads zero Bit 1:0 Reserved for Freescale’s internal use; always write zero MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 221 All other AD pins remain general purpose I/O pins Reset Initialize ADC ADCCFG = 0x98 ADCSC2 = 0x00 ADCSC1 = 0x41 Check COCO=1? Read ADCRH Then ADCRL To Clear COCO Bit Continue Figure 10-13. Initialization Flowchart for Example MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 222: Application Information

    Resistance in the REFH REFL path is not recommended because the current causes a voltage drop that could result in conversion errors. Inductance in this path must be minimum (parasitic only). MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 223: Sources Of Error

    If this error cannot be tolerated by the application, keep R lower than V / (2 ) for less than LEAK leakage error (N = 8 in 8-bit, 10 in 10-bit or 12 in 12-bit mode). MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 224 1/2 lsb in 8- or 10-bit mode. As a consequence, however, the code width of the first (0x000) conversion is only 1/2 lsb and the code width of the last (0xFF or 0x3FF) is 1.5 lsb. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 225 Non-monotonicity is defined as when, except for code jitter, the converter converts to a lower code for a higher input voltage. Missing codes are those values never converted for any input value. In 8-bit or 10-bit mode, the ADC is guaranteed to be monotonic and have no missing codes. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 226: Chapter 11 Internal Clock Source (S08Icsv3)

    NOTE The ICS on the MC9S08LG32 series is configured to support only the low and mid range DCO, therefore the DRS[1] and DRST[1] bits in ICSSC have no effect. The FLL will only multiply the reference clock by 512/1024 or 608/1216 depending on the state of the DMX32 bit.
  • Page 227 RX2/PTI0 VOLTAGE REGULATOR Available only on 80-pin package Available only on 64-pin and 80-pin package */Default function out of reset/* REFH REFL Figure 11-1. MC9S08LG32 Series Block Diagram Highlighting ICS Block and Pins MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 228: Features

    Three selectable digitally controlled oscillators (DCO) optimized for different frequency ranges. • Option to maximize output frequency for a 32768 Hz external reference clock source. 11.1.2 Block Diagram Figure 11-2 is the ICS block diagram. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 229: Modes Of Operation

    In FLL bypassed internal mode, the FLL is enabled and controlled by the internal reference clock, but is bypassed. The ICS supplies a clock derived from the internal reference clock. The BDC clock is supplied from the FLL. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 230: External Signal Description

    There are no ICS signals that connect off chip. 11.3 Register Definition Figure 11-1 is a summary of ICS registers. Table 11-1. ICS Register Summary Name ICSC1 CLKS RDIV IREFS IRCLKEN IREFSTEN ICSC2 BDIV RANGE EREFS ERCLKEN EREFSTEN ICSTRM TRIM MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 231: Ics Control Register 1 (Icsc1)

    ICS enters stop mode. 1 Internal reference clock stays enabled in stop if IRCLKEN is set before entering stop 0 Internal reference clock is disabled in stop Table 11-3. Reference Divide Factor RDIV RANGE=0 RANGE=1 1024 MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 232 Chapter 16 Internal Clock Source (S08ICSV3) Table 11-3. Reference Divide Factor RDIV RANGE=0 RANGE=1 Reserved Reserved Reset default MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 233: Ics Control Register 2 (Icsc2)

    Reset: Note: TRIM is loaded during reset from a factory programmed location when not in BDM mode. If in a BDM mode, a default value of 0x80 is loaded. Figure 11-5. ICS Trim Register (ICSTRM) MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 234: Ics Status And Control (Icssc)

    IREFS bit due to internal synchronization between clock domains. 0 Source of reference clock is external clock. 1 Source of reference clock is internal clock. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 235 39.85 MHz 31.25 - 39.0625 kHz 1536 48 - 60 MHz 32.768 kHz 1824 59.77 MHz Reserved The resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 236: Functional Description

    The FLL loop will lock the frequency to the FLL factor times the internal reference frequency. The ICSLCLK is available for BDC communications, and the internal reference clock is enabled. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 237 • RDIV bits are written to divide external reference clock to be within the range of 31.25 kHz to 39.0625 kHz. • BDM mode is active or LP bit is written to 0. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 238: Mode Switching

    DCO the FLL remains unlocked for several reference cycles. Once the selected DCO startup time is over, the FLL is locked. The completion of the switch is shown by the DRST bits. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 239: Bus Frequency Divider

    All MCU devices are factory programmed with a trim value in a reserved memory location. This value is uploaded to the ICSTRM register and ICS FTRIM register during any reset initialization. For finer precision, the user can trim the internal oscillator in the application and set the FTRIM bit accordingly. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 240: External Reference Clock

    The ICS presents the low range DCO output clock divided by two as ICSLCLK for use as a clock source for BDC communications. ICSLCLK is not available in FLL bypassed internal low-power (FBILP) and FLL bypassed external low-power (FBELP) modes. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 241: Chapter 12 Inter-Integrated Circuit (S08Iicv2)

    400 pF. NOTE • MC9S08LG32 series of MCUs include only one IIC module, therefore assume IICxA, IICxF, IICxC1, IICxS, IICxD, and IICxC2 register definitions as IIC0A, IIC0F, IIC0C1, IIC0S, IIC0D, and IIC0C2. •...
  • Page 242 RX2/PTI0 VOLTAGE REGULATOR Available only on 80-pin package Available only on 64-pin and 80-pin package */Default function out of reset/* REFH REFL Figure 12-1. MC9S08LG32 Series Block Diagram Highlighting IIC Block and Pins MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 243: Features

    Stop mode — The IIC is inactive in stop3 mode for reduced power consumption. The stop instruction does not affect IIC register states. Stop2 resets the register contents. 12.1.5 Block Diagram Figure 12-2 is a block diagram of the IIC. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 244: External Signal Description

    This section consists of the IIC register descriptions in address order. Refer to the direct-page register summary in Chapter 4, “Memory,” for the absolute address assignments for all IIC registers. This section refers to registers and control bits only by their names. A MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 245: Iic Address Register (Iicxa)

    Slave Address. The AD[7:1] field contains the slave address to be used by the IIC module. This field is used on AD[7:1] the 7-bit address scheme and the lower seven bits of the 10-bit address scheme. 12.3.2 IIC Frequency Divider Register (IICxF) MULT Reset Figure 12-4. IIC Frequency Divider Register (IICxF) MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 246 Table 12-4. Hold Time Values for 8 MHz Bus Speed Hold Times (μs) MULT SCL Start SCL Stop 0x00 3.500 3.000 5.500 0x07 2.500 4.000 5.250 0x0B 2.250 4.000 5.250 0x14 2.125 4.250 5.125 0x18 1.125 4.750 5.125 MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 247 (hex) Divider Value (hex) Divider Value Value Value Value Value 1024 1152 1280 1536 1920 1280 1536 1792 2048 1022 1025 2304 1150 1153 2560 1278 1281 3072 1534 1537 3840 1918 1921 MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 248: Iic Control Register (Iicxc1)

    Attempting a repeat at the wrong time results in loss of arbitration. 12.3.4 IIC Status Register (IICxS) IAAS BUSY RXAK ARBL IICIF Reset = Unimplemented or Reserved Figure 12-6. IIC Status Register (IICxS) MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 249: Iic Data I/O Register (Iicxd)

    If the RXAK bit is high it means that no acknowledge signal is detected. 0 Acknowledge received 1 No acknowledge received 12.3.5 IIC Data I/O Register (IICxD) DATA Reset Figure 12-7. IIC Data I/O Register (IICxD) MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 250: Iic Control Register 2 (Iicxc2)

    1 10-bit address scheme 2–0 Slave Address. The AD[10:8] field contains the upper three bits of the slave address in the 10-bit address AD[10:8] scheme. This field is only valid when the ADEXT bit is set. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 251: Functional Description

    SDA while SCL is high. This signal denotes the beginning of a new data transfer (each data transfer may contain several bytes of data) and brings all slaves out of their idle states. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 252 This is called repeated start. A stop signal is defined as a low-to-high transition of SDA while SCL at logical 1 (see Figure 12-9). The master can generate a stop even if the slave has generated an acknowledge at which point the slave must release the bus. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 253 The first device to complete its high period pulls the SCL line low again. Start Counting High Period Delay SCL1 SCL2 Internal Counter Reset Figure 12-10. IIC Clock Synchronization MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 254: 10-Bit Address

    A3. The slave-transmitter remains addressed until it receives a stop condition (P) or a repeated start condition (Sr) followed by a different slave address. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 255: General Call Address

    IICIE Arbitration Lost ARBL IICIF IICIE 12.6.1 Byte Transfer Interrupt The TCF (transfer complete flag) bit is set at the falling edge of the ninth clock to indicate the completion of byte transfer. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 256: Address Detect Interrupt

    A repeated start cycle is requested in slave mode. • A stop condition is detected when the master did not request it. This bit must be cleared by software writing a 1 to it. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 257: Initialization/Application Information

    ARBL IICIF RXAK IICS Module status flags DATA IICD Data register; Write to transmit IIC data read to read IIC data IICC2 GCAEN ADEXT AD10 Address configuration Figure 12-11. IIC Module Quick Start MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 258 When 10-bit addressing is used to address a slave, the slave sees an interrupt following the first byte of the extended address. User software must ensure that for this interrupt, the contents of IICD are ignored and not treated as a valid data transfer Figure 12-12. Typical IIC Interrupt Routine MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 259: Chapter 13 Serial Communications Interface (S08Sciv4)

    MC9S08LG32 series block diagram with the SCI highlighted. 13.1.1 Module Instances The MC9S08LG32 series MCUs contain two SCI modules: SCI1 and SCI2. The memory map, pins, interrupts, etc. for the two modules can be differentiated using the SCI1 and SCI2 nomenclature. 13.1.2...
  • Page 260 RX2/PTI0 VOLTAGE REGULATOR Available only on 80-pin package Available only on 64-pin and 80-pin package */Default function out of reset/* REFH REFL Figure 13-1. MC9S08LG32 Series Block Diagram Highlighting SCI Block and Pins MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 261: Features

    Selectable transmitter output polarity 13.1.5 Modes of Operation Section 13.3, “Functional Description,” for details concerning SCI operation in these modes: • 8- and 9-bit data modes • Stop mode operation • Loop mode • Single-wire mode MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 262: Block Diagram

    1 ¥ Baud Rate Clock Shift Direction TXINV Parity Generation SCI Controls TxD To TxD Transmit Control Pin Logic TxD Direction TXDIR BRK13 TDRE Tx Interrupt Request TCIE Figure 13-2. SCI Transmitter Block Diagram MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 263 Shift Direction WAKE Wakeup RWUID Logic Active Edge Detect RDRF IDLE ILIE Rx Interrupt Request LBKDIF LBKDIE RXEDGIF RXEDGIE ORIE FEIE Error Interrupt Request NEIE PARITY CHECKING PEIE Figure 13-3. SCI Receiver Block Diagram MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 264: Register Definition

    SCI baud rate generator. When BR is cleared, the SCI baud rate generator is disabled to reduce supply current. When BR is 1 – 8191, the SCI baud rate equals BUSCLK/(16×BR). See also BR bits Table 13-3. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 265: Sci Control Register 1 (Scixc1)

    0 Normal — start + 8 data bits (lsb first) + stop. 1 Receiver and transmitter use 9-bit data characters start + 8 data bits (lsb first) + 9th data bit + stop. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 266: Sci Control Register 2 (Scixc2)

    1 Hardware interrupt requested when RDRF flag is 1. Idle Line Interrupt Enable (for IDLE) ILIE 0 Hardware interrupts from IDLE disabled (use polling). 1 Hardware interrupt requested when IDLE flag is 1. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 267: Sci Status Register 1 (Scixs1)

    This register has eight read-only status flags. Writes have no effect. Special software sequences (which do not involve writing to this register) are used to clear these status flags. TDRE RDRF IDLE Reset = Unimplemented or Reserved Figure 13-8. SCI Status Register 1 (SCIxS1) MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 268 NF is set at the same time as RDRF is set for the character. To clear NF, read SCIxS1 and then read the SCI data register (SCIxD). 0 No noise detected. 1 Noise detected in the received character in SCIxD. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 269: Sci Status Register 2 (Scixs2)

    Detection of a framing error is not affected by the state of this bit. 0 Break character is transmitted with length of 10 bit times (11 if M = 1) 1 Break character is transmitted with length of 13 bit times (14 if M = 1) MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 270: Sci Control Register 3 (Scixc3)

    (LOOPS = RSRC = 1), this bit determines the direction of data at the TxD pin. 0 TxD pin is an input in single-wire mode. 1 TxD pin is an output in single-wire mode. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 271: Sci Data Register (Scixd)

    The following describes each of the blocks of the SCI. 13.3.1 Baud Rate Generation As shown in Figure 13-12, the clock source for the SCI baud rate generator is the bus-rate clock. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 272: Transmitter Functional Description

    If no new character is waiting in the transmit data buffer after a stop bit is shifted out the TxD pin, the transmitter sets the transmit complete flag and enters an idle mode, with TxD high, waiting for more characters to transmit. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 273: Receiver Functional Description

    (RDRF) status flag is set. If RDRF was already set indicating the receive data register (buffer) was already full, the MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 274 (with the exception of the idle bit, IDLE, when RWUID bit is set) are inhibited from setting, thus eliminating the software overhead for handling the unimportant message characters. At MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 275: Interrupts And Status Flags

    If the transmit complete interrupt enable (TCIE) bit is set, a hardware interrupt is requested when TC is set. Instead of hardware MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 276: Additional Sci Functions

    The 9-bit data mode is typically used with parity to allow eight bits of data plus the parity in the ninth bit, or it is used with address-mark wakeup so the ninth data bit can serve as the wakeup bit. In custom protocols, the ninth bit can also serve as a software-controlled marker. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 277 TxD pin is an output driven by the transmitter. In single-wire mode, the internal loop back connection from the transmitter to the receiver causes the receiver to receive characters that are sent out by the transmitter. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 278: Chapter 14 Serial Peripheral Interface (S08Spiv4)

    The SPI also supports a data length of 8 or 16 bits and includes a hardware match feature for the receive data buffer. Figure 14-1 shows the MC9S08LG32 series block diagram with the SPI block and pins highlighted. 14.1.1 Module Configuration...
  • Page 279 RX2/PTI0 VOLTAGE REGULATOR Available only on 80-pin package Available only on 64-pin and 80-pin package */Default function out of reset/* REFH REFL Figure 14-1. MC9S08LG32 series Block Diagram Highlighting SPI Block and Pins MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 280: Features

    (SS pin). In this system, the master device has configured its SS pin as an optional slave select output. SLAVE MASTER MOSI MOSI SPI SHIFTER SPI SHIFTER MISO MISO SPSCK SPSCK CLOCK GENERATOR Figure 14-2. SPI System Connections MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 281 MISO, and the shifter input is routed from the MOSI pin. In the external SPI system, simply connect all SPSCK pins to each other, all MISO pins together, and all MOSI pins together. Peripheral devices often use slightly different names for these pins. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 282: Spi Baud Rate Generation

    (SPPR2:SPPR1:SPPR0) choose a prescale divisor of 1, 2, 3, 4, 5, 6, 7, or 8. The three rate select bits (SPR3:SPR2:SPR1:SPR0) divide the output of the prescaler stage by 2, 4, 8, 16, 32, 64, 128, 256,or 512 to get the internal SPI master mode bit-rate clock. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 283: External Signal Description

    I/O pin. When the SPI is enabled as a master and MODFEN = 1, the slave select output enable bit determines whether this pin acts as the mode fault input (SSOE = 0) or as the slave select output (SSOE = 1). MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 284: Modes Of Operation

    SPI Transmit Interrupt Enable — This is the interrupt enable bit for SPI transmit buffer empty (SPTEF). SPTIE 0 Interrupts from SPTEF inhibited (use polling) 1 When SPTEF is 1, hardware interrupt requested MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 285: Spi Control Register 2 (Spixc2)

    This read/write register is used to control optional features of the SPI system. Bits 7, 6, 5, and 2 are not implemented and always read 0. MODFEN BIDIROE SPISWAI SPC0 Reset = Unimplemented or Reserved Figure 14-6. SPI Control Register 2 (SPIxC2) MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 286: Spi Baud Rate Register (Spixbr)

    SPI Baud Rate Divisor — This 4-bit field selects one of eight divisors for the SPI baud rate divider as shown in SPR[3:0] Table 14-7. The input to this divider comes from the SPI baud rate prescaler (see Figure 14-4). The output of this divider is the SPI bit rate clock for master mode. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 287: Spi Status Register (Spixs)

    This register has three read-only status bits. Bits 6, 3, 2, 1, and 0 are not implemented and always read 0. Writes have no meaning or effect. SPRF SPTEF MODF Reset = Unimplemented or Reserved Figure 14-8. SPI Status Register (SPIxS) MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 288: Spi Data Register (Spixd)

    Data may be read from SPIxD any time after SPRF is set and before another transfer is finished. Failure to read the data out of the receive data buffer before a new transfer ends causes a receive overrun condition and the data from the new transfer is lost. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 289: Functional Description

    SPSCK lines. In this case, the SPI immediately switches to slave mode, by clearing the MSTR bit and also disables the slave output buffer MISO (or SISO in bidirectional mode). So the result is that all outputs MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 290: Slave Mode

    For these simpler devices, there is no serial data out pin. NOTE When peripherals with duplex capability are used, take care not to simultaneously enable two receivers whose serial outputs drive the same system slave’s serial data output line. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 291: Spi Clock Formats

    SS output goes to active low one-half SPSCK cycle before the start of the transfer and goes back high at the end of the eighth bit time of the transfer. The SS IN waveform applies to the slave select input of a slave. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 292 (provided MODFEN and SSOE = 1). The master SS output goes to active low at the start of the first bit time of the transfer and goes back high one-half SPSCK cycle after MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 293: Special Features

    The SS output feature automatically drives the SS pin low during transmission to select external devices and drives it high during idle to deselect external devices. When SS output is selected, the SS output pin is connected to the SS input pin of the external device. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 294 The SPSCK is output for the master mode and input for the slave mode. The SS is the input or output for the master mode, and it is always the input for the slave mode. The bidirectional mode does not affect SPSCK and SS functions. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 295: Spi Interrupts

    MODF is cleared by reading it while it is set, then writing to the SPI control register 1 (SPIxC1). User software should verify the error condition has been corrected before changing the SPI back to master mode. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 296 Chapter 12 Serial Peripheral Interface (S08SPIV4) MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 297: Chapter 15 Real-Time Counter (S08Rtcv1)

    To conserve power, this bit can be cleared to disable the clock to this module when not in use. For more details, see Section 5.7, “Peripheral Clock Gating.” MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 298 RX2/PTI0 VOLTAGE REGULATOR Available only on 80-pin package Available only on 64-pin and 80-pin package */Default function out of reset/* REFH REFL Figure 15-1. MC9S08LG32 Series Block Diagram Highlighting RTC Block and Pins MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 299: Features

    The RTC suspends all counting during active background mode until the microcontroller returns to normal user operating mode. Counting resumes from the suspended value as long as the RTCMOD register is not written and the RTCPS and RTCLKS bits are not altered. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 300: Block Diagram

    RTC registers.This section refers to registers and control bits only by their names and relative address offsets. Table 15-1 is a summary of RTC registers. Table 15-1. RTC Register Summary Name RTCSC RTIF RTCLKS RTIE RTCPS RTCCNT RTCCNT RTCMOD RTCMOD MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 301: Rtc Status And Control Register (Rtcsc)

    See Table 15-3. Changing the prescaler value clears the prescaler and RTCCNT counters. Reset clears RTCPS. Table 15-3. RTC Prescaler Divide-by values RTCPS RTCLKS[0] 5x10 2x10 5x10 2x10 5x10 2x10 MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 302: Rtc Counter Register (Rtccnt)

    (OSCOUT), and the internal clock (IRCLK). The RTC clock select bits (RTCLKS) select the desired clock source. If a different value is written to RTCLKS, the prescaler and RTCCNT counters are reset to 0x00. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 303: Rtc Operation Example

    (RTIE) in RTCSC. RTIF is cleared by writing a 1 to RTIF. 15.4.1 RTC Operation Example This section shows an example of the RTC operation as the counter reaches a matching value from the modulo register. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 304: Initialization/Application Information

    /* Configure RTC to interrupt every 1 second from 1 kHz clock source */ RTCMOD.byte = 0x00; RTCSC.byte = 0x1F; /********************************************************************** Function Name : RTC_ISR Notes : Interrupt service routine for RTC module. **********************************************************************/ MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 305 Seconds = 0; /* 60 minutes in an hour */ if (Minutes > 59){ Hours++; Minutes = 0; /* 24 hours in a day */ if (Hours > 23){ Days ++; Hours = 0; MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 306: Chapter 16 Timer/Pulse-Width Modulator (S08Tpmv3)

    The TPM modules on the MC9S08LG32 series use the TPMCLK pin. 16.1.2 Module Instances The MC9S08LG32 series MCUs contain two TPM modules: TPM1 and TPM2. The memory map, pins, interrupts, etc. for the two modules can be differentiated using the TPM1 and TPM2 nomenclature. 16.1.3...

  • Page 307: Tpm Clock Gating

    RX2/PTI0 VOLTAGE REGULATOR Available only on 80-pin package Available only on 64-pin and 80-pin package */Default function out of reset/* REFH REFL Figure 16-1. MC9S08LG32 Series Block Diagram Highlighting TPMx Blocks and Pins MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 308: Features

    MCU pin. The output compare action is selected to force the pin to zero, force the pin to one, toggle the pin, or ignore the pin (used for software timing functions). • Edge-aligned PWM mode MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 309: Block Diagram

    (the values 0x0000 or 0xFFFF effectively make the counter free running). Software can read the counter value at any time without affecting the counting sequence. Any write to either half of the TPMxCNT counter resets the counter, regardless of the data value written. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 310 16-bit latch logic CH1IE MS1B MS1A up to 8 channels ELS7B ELS7A Port channel 7 TPMxCH7 logic 16-bit comparator TPMxC7VH:TPMxC7VL CH7F Interrupt 16-bit latch logic CH7IE MS7B MS7A Figure 16-2. TPM Block Diagram MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 311: Signal Description

    ELSnB:ELSnA ≠ 0:0), the TPMxCHn pin is forced to act as an edge-sensitive input to the TPM. ELSnB:ELSnA control bits determine what polarity edge or edges trigger input capture events. The channel input signal is synchronized on the bus clock. This implies the minimum pulse width—that can MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 312 PWM output signal. If ELSnB is set and ELSnA is cleared, the corresponding TPMxCHn pin is cleared when the TPM counter is counting up, and the channel value register matches the TPM counter; and it is MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 313 TPMxCHn CHnF bit TOF bit Figure 16-5. High-true pulse of a center-aligned PWM TPMxMODH:TPMxMODL = 0x0008 TPMxCnVH:TPMxCnVL = 0x0005 TPMxCNTH:TPMxCNTL TPMxCHn CHnF bit TOF bit Figure 16-6. Low-true pulse of a center-aligned PWM MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 314: Register Definition

    TPM counter. The new prescale factor affects the selected clock on the next bus clock cycle after the new value is updated into the register bits. Table 16-4. TPM Clock Selection CLKSB:CLKSA TPM Clock to Prescaler Input No clock selected (TPM counter disable) Bus clock MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 315: Tpm-Counter Registers (Tpmxcnth:tpmxcntl)

    Any write to TPMxCNTH clears the 16-bit counter Reset Figure 16-8. TPM Counter Register High (TPMxCNTH) TPMxCNT[7:0] Any write to TPMxCNTL clears the 16-bit counter Reset Figure 16-9. TPM Counter Register Low (TPMxCNTL) MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 316: Tpm Counter Modulo Registers (Tpmxmodh:tpmxmodl)

    BDM is active. TPMxMOD[15:8] Reset Figure 16-10. TPM Counter Modulo Register High (TPMxMODH) TPMxMOD[7:0] Reset Figure 16-11. TPM Counter Modulo Register Low (TPMxMODL) MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 317: Tpm Channel N Status And Control Register (Tpmxcnsc)

    If ELSnB and ELSnA bits are cleared, the channel pin is not controlled by TPM. This configuration can be used by software compare only, because it does not require the use of a pin for the channel. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 318: Tpm Channel Value Registers (Tpmxcnvh:tpmxcnvl)

    This latching mechanism also resets (becomes unlatched) when the TPMxCnSC register is written (whether BDM mode is active or not). Any write to the channel registers is ignored during the input capture mode. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 319: Functional Description

    The following sections describe TPM counter and each of the timer operating modes (input capture, output compare, edge-aligned PWM, and center-aligned PWM). Because details of pin operation and interrupt MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 320: Counter

    (at the transition from the value set in the modulus register to the next lower count value). This corresponds to the end of a PWM period (the 0x0000 count value corresponds to the center of a period). MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 321: Channel Mode Selection

    With the output compare function, the TPM can generate timed pulses with programmable position, polarity, duration, and frequency. When the counter reaches the value in TPMxCnVH:TPMxCnVL registers of an output compare channel, the TPM can set, clear, or toggle the channel pin. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 322 If CLKSB and CLKSA are cleared, the registers are updated when the second byte is written • If CLKSB and CLKSA are not cleared, the registers are updated after both bytes were written, and the TPM counter changes from (TPMxMODH:TPMxMODL – 1) to MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 323 Center-aligned PWM outputs typically produce less noise than edge-aligned PWMs because fewer I/O pin transitions are lined up at the same system clock edge. This type of PWM is also required for some types of motor drives. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 324: Reset Overview

    If the channel is configured for output compare or PWM modes, the interrupt flag is set each time the main timer counter matches the value in the 16-bit channel value register. All TPM interrupts are listed in Table 16-8. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 325: Description Of Interrupt Operation

    (the value in the modulo register). 16.6.2.2 Channel Event Interrupt Description The meaning of channel interrupts depends on the channel’s current mode (input capture, output compare, edge-aligned PWM, or center-aligned PWM). MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 326 PWM cycle. In this CPWM case, the channel flag is set at the start and at the end of the active duty cycle period when the timer counter matches the channel value register. The flag is cleared by the two-step sequence described in Section 16.6.2, “Description of Interrupt Operation.” MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 327: Chapter 17 Modulo Timer (S08Mtimv1)

    A timer overflow interrupt can be enabled to generate periodic interrupts for time-based software loops. Figure 17-1 shows the MC9S08LG32 series block diagram highlighting the MTIM block and pin. 17.1.1 MTIM Clock Gating The bus clock to the MTIM can be gated on and off using the MTIM bit in SCGC1. This bit is cleared after any reset, which disables the bus clock to this module.
  • Page 328 RX2/PTI0 VOLTAGE REGULATOR Available only on 80-pin package Available only on 64-pin and 80-pin package */Default function out of reset/* REFH REFL Figure 17-1. MC9S08LG32 Series Block Diagram Highlighting MTIM Block and Pins MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 329: Features

    The MTIM suspends all counting until the microcontroller returns to normal user operating mode. Counting resumes from the suspended value as long as an MTIM reset did not occur (TRST written to a 1 MOD written). MTIM MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 330: Block Diagram

    Therefore, the TPMCLK signal must be limited to one-fourth of the bus frequency. The TPMCLK pin can be muxed with a general-purpose port pin. See the Chapter 2, “Pins and Connections,” chapter for the pin location and priority of this function. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 331: Memory Map And Register Definition

    Refer to the direct-page register summary in the Chapter 4, “Memory,” for the absolute address assignments for all MTIM registers.This section refers to registers and control bits only by their names and relative address offsets. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 332 Unused register bits, always read 0. 17.3.2.2 MTIM Clock Configuration Register (MTIMCLK) MTIMCLK contains the clock select bits (CLKS) and the prescaler select bits (PS). CLKS Reset: Figure 17-5. MTIM Clock Configuration Register (MTIMCLK) MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 333 Table 17-4. MTIMCNT Field Descriptions Field Description MTIM Count — These eight read-only bits contain the current value of the 8-bit counter. Writes have no effect to COUNT this register. Reset clears the count to $00. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 334 MTIM Modulo — These eight read/write bits contain the modulo value used to reset the count and set TOF. A value of $00 puts the MTIM in free-running mode. Writing to MTIMMOD resets the COUNT to $00 and clears TOF. Reset sets the modulo to $00. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 335: Functional Description

    MTIM overflow interrupt enable bit (TOIE) in MTIMSC. TOIE should never be written to a 1 while TOF = 1. Instead, TOF should be cleared first, then the TOIE can be set to 1. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 336: Mtim Operation Example

    CNT, reaches the modulo value of $AA, the counter overflows to $00 and MTIM continues counting. The timer overflow flag, TOF, sets when the counter value changes from $AA to $00. An MTIM overflow interrupt is generated when TOF is set, if TOIE = 1. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 337: Chapter 18 Development Support

    The method for forcing active background mode depends on the specific HCS08 derivative. For the MC9S08LG32 series, you can force active background after a power-on reset by holding the BKGD pin low as the device exits the reset condition. You can also force active background by driving BKGD low immediately after a serial background command that writes a one to the BDFR bit in the SBDFR register.

  • Page 338: Features

    However, if the pod is powered separately, it can be connected to a running target system without forcing a target system reset or otherwise disturbing the running application program. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 339: Bkgd Pin Description

    MSB first at 16 BDC clock cycles per bit (nominal speed). The interface times out if 512 BDC clock cycles occur between falling edges from the host. Any BDC command that was in progress MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 340 (TARGET MCU) HOST TRANSMIT 1 HOST TRANSMIT 0 10 CYCLES EARLIEST START OF NEXT BIT SYNCHRONIZATION TARGET SENSES BIT LEVEL UNCERTAINTY PERCEIVED START OF BIT TIME Figure 18-2. BDC Host-to-Target Serial Bit Timing MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 341 HIGH-IMPEDANCE HIGH-IMPEDANCE PERCEIVED START OF BIT TIME R-C RISE BKGD PIN 10 CYCLES EARLIEST START OF NEXT BIT 10 CYCLES HOST SAMPLES BKGD PIN Figure 18-3. BDC Target-to-Host Serial Bit Timing (Logic 1) MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 342 DRIVE AND SPEED-UP PULSE PERCEIVED START OF BIT TIME BKGD PIN 10 CYCLES EARLIEST START OF NEXT BIT 10 CYCLES HOST SAMPLES BKGD PIN Figure 18-4. BDM Target-to-Host Serial Bit Timing (Logic 0) MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 343: Bdc Commands

    8 bits of write data for BDCSCR in the host-to-target direction (CONTROL) RBKP 16 bits of read data in the target-to-host direction (from BDCBKPT breakpoint register) WBKP 16 bits of write data in the host-to-target direction (for BDCBKPT breakpoint register) MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 344 H:X Increment H:X by one, then write memory byte WRITE_NEXT_WS Active BDM 51/WD/d/SS located at H:X. Also report status. The SYNC command is a special operation that does not have a command code. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 345: Bdc Hardware Breakpoint

    The force/tag select (FTS) control bit in BDCSCR is used to select forced (FTS = 1) or tagged (FTS = 0) type breakpoints. 18.3 Register Definition This section contains the descriptions of the BDC registers and control bits. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 346: Bdc Registers And Control Bits

    MCU is already in active background mode.) Also, the four status bits (BDMACT, WS, WSF, and DVF) are read-only status indicators and can never be written by the WRITE_CONTROL serial BDC command. The clock switch (CLKSW) control bit may be read or written at any time. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 347 1 Breakpoint match forces active background mode at next instruction boundary (address need not be an opcode) Select Source for BDC Communications Clock — CLKSW defaults to 0, which selects the alternate BDC clock CLKSW source. 0 Alternate BDC clock source 1 MCU bus clock MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 348: System Background Debug Force Reset Register (Sbdfr)

    0 Memory access did not conflict with a wait or stop instruction 1 Memory access command failed because the CPU entered wait or stop mode Data Valid Failure Status — This status bit is not used in the MC9S08LG32 series because it does not have any slow access memory.
  • Page 349 Background Debug Force Reset — A serial active background mode command such as WRITE_BYTE allows BDFR an external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot be written from a user program. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 350: Chapter 19 Debug Module (Dbg) (64K)

    — Source address of conditional branches taken — Destination address of indirect JMP and JSR instruction — Destination address of interrupts, RTI, RTC, and RTS instruction — Data associated with Event B trigger modes MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 351: Modes Of Operation

    Write Data Bus Read Data Bus Read/Write 1. In 64K versions of this module there are only 16 address lines [15:0], there are no core_cpu_aob_14_t2, core_cpu_aob_15_t2, core_ppage_t2[2:0], and ppage_sel signals. Figure 19-1. DBG Block Diagram MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 352: Signal Description

    Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DBGCCH Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 353 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DBGCAX RWAEN DBGCBX RWBEN DBGCCX RWCEN reserved DBGC DBGEN BRKEN LOOP1 DBGT TRGSEL BEGIN TRG[3:0] DBGS ARMF DBGCNT CNT[3:0] MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 354: Register Descriptions

    Reset end-run Figure 19-3. Debug Comparator A Low Register (DBGCAL) In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the bits in this register do not change after reset. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 355 Module Base + 0x0003 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 or non- end-run Reset end-run Figure 19-5. Debug Comparator B Low Register (DBGCBL) MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 356 Comparator C High Compare Bits — The Comparator C High compare bits control whether Comparator C will compare the address bus bits [15:8] to a logic 1 or logic 0. 0 Compare corresponding address bit to a logic 0 1 Compare corresponding address bit to a logic 1 MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 357 FIFO High Data Bits — The FIFO High data bits provide access to bits [15:8] of data in the FIFO. This register is not used in event only modes and will read a $00 for valid FIFO words. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 358 = Unimplemented or Reserved Figure 19-10. Debug Comparator A Extension Register (DBGCAX) In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the bits in this register do not change after reset. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 359 Comparator B. The RWB bit is not used if RWBEN = 0. In full modes, RWAEN and RWA are used to control comparison of R/W and RWB is ignored. 0 Write cycle will be matched 1 Read cycle will be matched MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 360 Read/Write Comparator C Value Bit — The RWC bit controls whether read or write is used in compare for Comparator C. The RWC bit is not used if RWCEN = 0. 0 Write cycle will be matched 1 Read cycle will be matched MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 361 COF address with the address in comparator C. If these addresses match, override the FIFO capture and do not increment the FIFO count. If the address does not match comparator C, capture the COF address, including the PPACC indicator, into the FIFO and into comparator C. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 362 0010 A Then B 0011 Event Only B 0100 A Then Event Only B 0101 A And B (Full Mode) 0110 A And Not B (Full mode) 0111 Inside Range 1000 Outside Range MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 363 While DBGEN = 1, this status bit is a read-only image of the ARM bit in DBGC. See Section 19.4.4.2, “Arming the DBG Module,” for more information. 0 Debugger not armed 1 Debugger armed MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 364 No data valid 0001 1 word valid 0010 2 words valid 0011 3 words valid 0100 4 words valid 0101 5 words valid 0110 6 words valid 0111 7 words valid 1000 8 words valid MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 365: Functional Description

    CPU will occur. If the BEGIN bit is set, begin-trigger is selected and the breakpoint request will not occur until the FIFO is filled with 8 words. If the BEGIN bit is cleared, end-trigger is selected and the breakpoint request will occur immediately at the trigger cycle. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 366: Trigger Selection

    The TRGSEL bit in DBGT controls whether a comparator A or B match is further qualified by opcode tracking logic. Each comparator has a separate circuit to track opcodes because the comparators could MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 367 19-16. The trigger mode is used as a qualifier for either starting or ending the storing of data in the FIFO. When the match condition is met, the appropriate flag AF or BF is set in DBGS register. Arming MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 368 Not B occur no flags are set. For Breakpoint tagging operation with an end-trigger type trace, only matches from Comparator A will be used to determine if the Breakpoint conditions are met and Comparator B matches will be ignored. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 369 4 In begin trace configurations (BEGIN = 1) where a CPU breakpoint is enabled (BRKEN = 1), TAG should not be set to 1. In begin trace debug runs, the CPU breakpoint corresponds to the FIFO full condition which does not correspond to a taggable instruction fetch. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 370: Fifo

    The FIFO is normally only read while ARM and ARMF=0, however reading the FIFO while the DBG module is armed will return the data value in the oldest location of the FIFO and the TBC will not allow MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...

  • Page 371: Interrupt Priority

    0xFFFE appears during the reset vector fetch • DBGC=0xC0 to enable and arm the DBG module • DBGT=0x40 to select a force-type trigger, a BEGIN trigger, and A-only trigger mode 19.6 Interrupts The DBG contains no interrupt source. MC9S08LG32 MCU Series, Rev. 5 Freescale Semiconductor...
  • Page 373 All other product or service names are the property of their respective owners. +86 10 5879 8000 © Freescale Semiconductor, Inc. 2009. All rights reserved. support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com MC9S08LG32 Rev. 5, 8/2009...

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