Memory Map And Register Definition - NXP Semiconductors MC9S08SU16 Reference Manual

Memory map and register definition

Table 11-38. Set factory margin level command error handling
Register
FSTAT
Factory margin levels must only be used during verify of the
initial factory programming.
Factory margin levels can be used to check that Flash memory
contents have adequate margin for data retention at the normal
level setting. If unexpected results are encountered when
checking flash memory contents at factory margin levels, the
fash memory contents must be erased and reprogrammed.
11.4 Memory map and register definition
This section presents a high-level summary of the registers and how they are mapped.
The registers can be accessed in 32-bits, 16-bits (aligned on data[31:16] or on data[15:0])
or 8-bits. In the case of the writable registers, the write accesses are forbidden during
flash command execution. For more details, see Caution note in
Absolute
address
(hex)
1830 Flash Clock Divider Register (FTMRH_FCLKDIV)
1831 Flash Security Register (FTMRH_FSEC)
1832 Flash CCOB Index Register (FTMRH_FCCOBIX)
1834 Flash Configuration Register (FTMRH_FCNFG)
1836 Flash Status Register (FTMRH_FSTAT)
1838 Flash Protection Register (FTMRH_FPROT)
Flash Common Command Object Register:High
183A
(FTMRH_FCCOBHI)
180
Error bit Error condition
Set if CCOBIX[2:0] != 010 at command launch
Set if command is not available in current mode (see
ACCERR
Set if an invalid global address [23:0] is supplied
Set if an invalid margin level setting is supplied
FPVIOL None
MGSTAT1 None
MGSTAT0 None
CAUTION
Note
FTMRH memory map
Register name
Table continues on the next page...
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Table
Flash memory
Width
Access Reset value
(in bits)
8 R/W 00h
8 R Undefined
8 R/W 00h
8 R/W 00h
8 R/W 80h
8 R See section
8 R/W 00h
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