Memory Map And Register Definition - NXP Semiconductors MC9S08SU16 Reference Manual

Memory map and register definition

25.6 Memory map and register definition
This section includes the module memory map and detailed descriptions of all registers.
Absolute
address
(hex)
20 PHCMP0 Control Register 0 (GDU_PHCMP0CR0)
21 PHCMP0 Control Register 1 (GDU_PHCMP0CR1)
22 PHCMP0 Filter Period Register (GDU_PHCMP0FPR)
23 PHCMP0 Status and Control Register (GDU_PHCMP0SCR)
24 PHCMP1 Control Register 0 (GDU_PHCMP1CR0)
25 PHCMP1 Control Register 1 (GDU_PHCMP1CR1)
26 PHCMP1 Filter Period Register (GDU_PHCMP1FPR)
27 PHCMP1 Status and Control Register (GDU_PHCMP1SCR)
28 PHCMP2 Control Register 0 (GDU_PHCMP2CR0)
29 PHCMP2 Control Register 1 (GDU_PHCMP2CR1)
2A PHCMP2 Filter Period Register (GDU_PHCMP2FPR)
2B PHCMP2 Status and Control Register (GDU_PHCMP2SCR)
1870 Clamp Control Register (GDU_CLMPCTRL)
1871 I/O Control Register (GDU_IOCTRL)
Virtual Network Phase Detection Control
1872
(GDU_PHASECTRL)
Current Sensor and Overcurrent Protection Control Register
1873
(GDU_CURCTRL)
1874 LIMIT0 CMP Control Register 0 (GDU_LIMIT0CR0)
1875 LIMIT0 CMP Control Register 1 (GDU_LIMIT0CR1)
1876 LIMIT0 CMP Filter Period Register (GDU_LIMIT0FPR)
LIMIT0 CMP Status and Control Register
1877
(GDU_LIMIT0SCR)
1878 LIMIT0 DAC Control Register (GDU_LIMIT0DACCR)
1879 LIMIT1 CMP Control Register 0 (GDU_LIMIT1CR0)
187A LIMIT1 CMP Control Register 1 (GDU_LIMIT1CR1)
187B LIMIT1 CMP Filter Period Register (GDU_LIMIT1FPR)
LIMIT1 CMP Status and Control Register
187C
(GDU_LIMIT1SCR)
187D LIMIT1 DAC Control Register (GDU_LIMIT1DACCR)
187E PDCS and Clamp Status Register (GDU_STATREG)
187F LIMIT CMP BIAS Register (GDU_SIGBIAS)
438
GDU memory map
Register name
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Width
Access Reset value
(in bits)
8 R/W 00h
8 R/W 00h
8 R/W 00h
8 R/W 00h
8 R/W 00h
8 R/W 00h
8 R/W 00h
8 R/W 00h
8 R/W 00h
8 R/W 00h
8 R/W 00h
8 R/W 00h
8 R/W 86h
8 R/W 01h
8 R/W 00h
8 R/W 00h
8 R/W 00h
8 R/W 00h
8 R/W 00h
8 R/W 00h
8 R/W 00h
8 R/W 00h
8 R/W 00h
8 R/W 00h
8 R/W 00h
8 R/W 00h
8 R 00h
8 R/W 00h
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