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Chapter 9
System Integration Module (SIM)
9.1 Chip specific windowed COP
The windowed COP (WCOP) module triggers a system reset if it is allowed to time out.
The program is expected to periodically reload the COP timer, thereby preventing it from
timing out. However, if a fault occurs that causes the program to stop working, the timer
will not be reloaded and it will time out. The resulting trigger of a system reset brings the
system back from an unresponsive state into a normal state.
After any reset, the WCOP is enabled. If the WCOP is not used in an application, it can
be disabled by clearing SIM_SOPT1[COPT].
The WCOP counter is reset by writing 0x55 and 0xAA (in that order) to the address of
the SIM_SRS during the selected timeout period. Writes do not affect the data in that
field. As soon as the write sequence is complete, the WCOP timeout period is restarted. If
the program fails to perform this restart during the timeout period, the microcontroller
resets. Also, if any value other than 0x55 or 0xAA is written to the SIM_SRS register, the
microcontroller immediately resets.
Windowed watchdog operation is available by setting SIM_SOPT1[COPW], In this
mode, writes to service watchdog register SIM_SRS to clear WCOP counter must be in a
selected timeout period. A premature write immediately resets the chip.
WCOP has four clock selections: BUSCLK (20 MHz), ICSIRCLK (up to the 32 kHz)
and an independent clock source LPOCLK (up to the 20 kHz), CLKIN
Customization:
• Primary clock: BUSCLK (20 MHz)
• Input clock option: BUSCLK (20 MHz); ICSIRCLK (up to the 32 kHz), LPOCLK
(up to the 20 kHz), CLKIN (40 MHz)
• WCOP is a part of SIM. Its register set is a subset of SIM registers.
Module Instances:
• One
NXP Semiconductors
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
97
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