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Field
This read/write flag is set at the beginning of every reload cycle regardless of the state of the LDOK bit.
Clear PWMF by reading PWM control register with PWMF set and then writing a zero to the PWMF bit. If
another reload occurs before the clearing sequence is complete, writing zero to PWMF has no effect.
Reset clears PWMF.
NOTE: Clearing PWMF clears pending PWMF interrupt requests.
0
No new reload cycle since last PWMF clearing.
1
New reload cycle since last PWMF clearing.
3–2
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
1
Load Okay
LDOK
This read/write bit loads the prescaler bits of CTRL and the entire PMMCM and VAL registers into a set of
buffers. The buffered prescaler divisor, PWM counter modulus value, and PWM pulse width take effect at
the next PWM reload. Set LDOK by writing a one to it. LDOK is automatically cleared after the new values
are loaded, or can be manually cleared before a reload by writing a zero to it. Reset clears LDOK.
0
Do not load new modulus, prescaler, and PWM values.
1
Load prescaler, modulus, and PWM values.
0
PWM Enable
PWMEN
This read/write bit enables the PWM generator and the PWM pins. When PWMEN equals zero, the PWM
pins are in their inactive states unless OUTCTLn equals one. A reset clears PWMEN.
0
PWM generator and PWM pins disabled unless OUTCTL = 1.
1
PWM generator and PWM pins enabled.
26.4.2 PWM Control Register: High (PWM_CTRLH)
Address: 40h base + 1h offset = 41h
Bit
7
Read
Write
Reset
0
Field
7–4
Load Frequency Bits
LDFQ
These buffered read/write bits select the PWM load frequency according to the table below. Reset clears
the LDFQ bits, selecting loading every PWM opportunity. A PWM opportunity is determined by the half bit.
NOTE: The LDFQn bits take effect when the current load cycle is complete, regardless of the state of the
0000
Every PWM opportunity
0001
Every 2 PWM opportunities
NXP Semiconductors
PWM_CTRLL field descriptions (continued)
6
5
LDFQ
0
0
PWM_CTRLH field descriptions
load okay bit, LDOK. Reading the LDFQn bits reads the buffered values and not necessarily the
values currently in effect.
Table continues on the next page...
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 26 Pulse Width Modulator (PWM)
Description
4
3
HALF
0
0
Description
2
1
0
0
0
0
0
507
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