Center-Aligned Pwm (Cpwm) Mode - NXP Semiconductors MC9S08SU16 Reference Manual

Functional Description
MODH:L = 0x0008
CnVH:L = 0x0005
channel (n) output
Figure 19-12. EPWM signal with ELSnB:ELSnA = 1:0
If (ELSnB:ELSnA = X:1), then the channel (n) output is forced low at the counter
overflow, when the value of 0x0000 is loaded into the FTM counter. Additionally, it is
forced high at the channel (n) match, when the FTM counter = CnVH:L. See the
following figure.
MODH:L = 0x0008
CnVH:L = 0x0005
channel (n) output
Figure 19-13. EPWM signal with ELSnB:ELSnA = X:1
If (CnVH:L = 0x0000), then the channel (n) output is a 0% duty cycle EPWM signal and
CHnF bit is not set, even when there is the channel (n) match. If (CnVH:L > MODH:L),
then the channel (n) output is a 100% duty cycle EPWM signal and CHnF bit is not set,
even when there is the channel (n) match. Therefore, MODH:MODL must be less than
0xFFFF in order to get a 100% duty cycle EPWM signal.

19.5.7 Center-aligned PWM (CPWM) mode

The center-aligned mode is selected when:
• (CPWMS = 1)
The CPWM pulse width (duty cycle) is determined by 2 × (CnVH:L). The period is
determined by 2 × (MODH:L). See the following figure. MODH:L must be kept in the
range of 0x0001 to 0x7FFF because values outside this range can produce ambiguous
results.
In the CPWM mode, the FTM counter counts up until it reaches MODH:L and then
counts down until it reaches the value of 0x0000.
336
counter
overflow
CNTH:L 0 1 2
...
CHnF bit previous value
TOF bit
counter
overflow
CNTH:L 0 1 2
...
previous value
CHnF bit
TOF bit
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
channel (n)
counter
match overflow
3 4 5 6 7 8 0
channel (n) counter
match overflow
3 4 5 6 7 8 0
1 2
...
1 2
...
NXP Semiconductors