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Memory map and registers
Absolute
address
(hex)
18C0
Debug Comparator A High Register (DBG_CAH)
18C1
Debug Comparator A Low Register (DBG_CAL)
18C2
Debug Comparator B High Register (DBG_CBH)
18C3
Debug Comparator B Low Register (DBG_CBL)
18C4
Debug Comparator C High Register (DBG_CCH)
18C5
Debug Comparator C Low Register (DBG_CCL)
18C6
Debug FIFO High Register (DBG_FH)
18C7
Debug FIFO Low Register (DBG_FL)
18C8
Debug Comparator A Extension Register (DBG_CAX)
18C9
Debug Comparator B Extension Register (DBG_CBX)
18CA
Debug Comparator C Extension Register (DBG_CCX)
18CB
Debug FIFO Extended Information Register (DBG_FX)
18CC
Debug Control Register (DBG_C)
18CD
Debug Trigger Register (DBG_T)
18CE
Debug Status Register (DBG_S)
18CF
Debug Count Status Register (DBG_CNT)
28.3.1 Debug Comparator A High Register (DBG_CAH)
All the bits in this register reset to 1 in POR or non-end-run
reset. The bits are undefined in end-run reset. In the case of an
end-trace to reset where DBGEN = 1 and BEGIN = 0, the bits
in this register do not change after reset.
Address: 18C0h base + 0h offset = 18C0h
Bit
7
Read
Write
Reset
1
552
DBG memory map
Register name
NOTE
6
5
1
1
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Width
Access
(in bits)
8
R/W
8
R/W
8
R/W
8
R/W
8
R/W
8
R/W
8
8
8
R/W
8
R/W
8
R/W
8
8
R/W
8
R/W
8
8
4
3
CA[15:8]
1
1
Section/
Reset value
page
FFh
28.3.1/552
FEh
28.3.2/553
00h
28.3.3/554
00h
28.3.4/554
00h
28.3.5/555
00h
28.3.6/556
R
00h
28.3.7/556
R
00h
28.3.8/557
00h
28.3.9/558
28.3.10/
00h
559
28.3.11/
00h
560
28.3.12/
R
00h
561
28.3.13/
C0h
561
28.3.14/
40h
562
28.3.15/
R
01h
564
28.3.16/
R
00h
565
2
1
1
1
NXP Semiconductors
0
1
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