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The DBG trigger register (DBGT) can not be changed unless
ARM=0.
Address: 18C0h base + Dh offset = 18CDh
Bit
7
Read
TRGSEL
Write
Reset
0
Field
7
Trigger Selection Bit
TRGSEL
The TRGSEL bit controls the triggering condition for the comparators.
0
Trigger on any compare address access.
1
Trigger if opcode at compare address is execute.
6
Begin/End Trigger Bit
BEGIN
The BEGIN bit controls whether the trigger begins or ends storing of data in FIFO.
0
Trigger at end of stored data.
1
Trigger before storing data.
5–4
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
TRG
Trigger Mode Bits
The TRG bits select the trigger mode of the DBG module.
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001-1111
NXP Semiconductors
NOTE
6
5
0
BEGIN
1
0
DBG_T field descriptions
A only.
A or B.
A then B.
Event only B.
A then event only B.
A and B (full mode).
A and not B (full mode).
Inside range.
Outside range.
No trigger.
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
4
3
0
0
Description
Chapter 28 Debug module (DBG)
2
1
TRG
0
0
0
0
563
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