NXP Semiconductors MC9S08SU16 Reference Manual page 146

Instruction Set Summary
Source Form Operation
BSET n,opr8a Set Bit n in Memory
BSR rel Branch to Subroutine
CBEQ opr8a,rel
CBEQA
#opr8i,rel
CBEQX Compare and Branch
#opr8i,rel if Equal
CBEQ oprx8,X
+,rel
CBEQ ,X+,rel
CBEQ
oprx8,SP,rel
CLC Clear Carry Bit
CLI Clear Interrupt Mask
CLR opr8a
CLRA
CLRX
CLRH
CLR oprx8,X
CLR ,X
CLR oprx8,SP
CMP #opr8i
CMP opr8a
CMP opr16a
CMP oprx16,X
Compare Accumulator
CMP oprx8,X
with Memory
CMP ,X
CMP oprx16,SP
146
Table 10-3. Instruction Set Summary (continued)
Description
Mn ← 1
PC ← (PC) + 0x0002
push (PCL)
SP ← (SP) – 0x0001
push (PCH)
SP ← (SP) – 0x0001
PC ← (PC) + rel
Branch if (A) = (M)
Branch if (A) = (M)
Branch if (X) = (M)
Branch if (A) = (M)
Branch if (A) = (M)
Branch if (A) = (M)
C ← 0
I ← 0
Bit
M ← 0x00
A ← 0x00
X ← 0x00
H ← 0x00
Clear
M ← 0x00
M ← 0x00
M ← 0x00
(A) – (M); (CCR
Updated But Operands
Not Changed)
Table continues on the next page...
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Effect on CCR
Address
V H I N Z C
Mode
– – – – – – DIR (b3)
– – – – – – DIR (b4)
– – – – – – DIR (b5)
– – – – – – DIR (b6)
– – – – – – DIR (b7)
– – – – – – REL
– – – – – – DIR
– – – – – – IMM
– – – – – – IMM
– – – – – – IX1+
– – – – – – IX+
– – – – – – SP1
– – – – – 0 INH
– – 0 – – – INH
0 – – 0 1 – DIR
0 – – 0 1 – INH
0 – – 0 1 – INH
0 – – 0 1 – INH
0 – – 0 1 – IX1
0 – – 0 1 – IX
0 – – 0 1 – SP1
– – IMM
↕ ↕ ↕ ↕
– – DIR
↕ ↕ ↕ ↕
– – EXT
↕ ↕ ↕ ↕
– – IX2
↕ ↕ ↕ ↕
– – IX1
↕ ↕ ↕ ↕
– – IX
↕ ↕ ↕ ↕
– – SP2
↕ ↕ ↕ ↕
16 dd 5
18 dd 5
1A dd 5
1C dd 5
1E dd 5
AD rr 5
31 dd rr 5
41 ii rr 4
51 ii rr 4
61 ff rr 5
71 rr 5
9E61 ff rr 6
98 1
9A 1
3F dd 5
4F 1
5F 1
8C 1
6F ff 5
7F 4
9E6F ff 6
A1 ii 2
B1 dd 3
C1 hh ll 4
D1 ee ff 4
E1 ff 3
F1 3
9ED1 ee ff 5
NXP Semiconductors