Independent Or Complementary Channel Operation - NXP Semiconductors MC9S08SU16 Reference Manual

26.3.3 Independent or complementary channel operation

In the CNFG register, writing 1 to the independent (INDEPnn) or complement pair
operation bit configures a pair of the PWM outputs as two independent PWM channels.
Each PWM output has its own PWM value register operating independently of the other
channels in independent channel operation.
Writing 0 to the INDEPnn bit configures the PWM output as a pair of complementary
channels. The PWM pins are paired in complementary channel operation, illustrated in
the following figure.
NXP Semiconductors
4
3
2
Up Counter
Modulus = 4
1
PWM Value = 0
0/4 = 0%
PWM Value = 1
1/4 = 25%
PWM Value = 2
2/4 = 50%
PWM Value = 3
3/4 = 75%
PWM Value = 4
4/4 = 100%
Figure 26-8. Edge-Aligned PWM pulse width
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 26 Pulse Width Modulator (PWM)
489