Configuration Options; Edge And Level Sensitivity; Irq Memory Map And Register Descriptions; Interrupt Pin Request Status And Control Register (Irq_Sc) - NXP Semiconductors MC9S08SU16 Reference Manual

4.3.1.1 Configuration options

The IRQ input enable control bit (IRQSC[IRQPE]) must be 1 for the IRQ signal to act as
the IRQ input. The user can choose the polarity of edges or levels detected (IRQEDG),
whether the pin detects edges-only or edges and levels (IRQMOD), or whether an event
causes an interrupt or only sets the IRQF flag, which can be polled by software.
Since IRQ signal is from XBAR_OUT15, it is recommend XBAR_OUT15 is set to logic
high after reset.
BIH and BIL instructions may be used to detect the level on the IRQ signal when IRQ is
enabled.

4.3.1.2 Edge and level sensitivity

The IRQSC[IRQMOD] control bit reconfigures the detection logic so that it can detect
edge events and levels. In this detection mode, the IRQF status flag is set when an edge is
detected, if the IRQ signal changes from the de-asserted to the asserted level, but the flag
is continuously set and cannot be cleared as long as the IRQ signal remains at the asserted
level.
4.4

IRQ Memory Map and Register Descriptions

Absolute
address
(hex)
7F

Interrupt Pin Request Status and Control Register (IRQ_SC)

4.4.1 Interrupt Pin Request Status and Control Register (IRQ_SC)
This direct page register includes status and control bits, which are used to configure the
IRQ function, report status, and acknowledge IRQ events.
Address: 7Fh base + 0h offset = 7Fh
Bit 7
Read 0
Write
Reset
0
NXP Semiconductors
IRQ memory map
Register name
6 5
IRQPDD IRQEDG
0 0
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Width
(in bits)
8
4 3
IRQF
IRQPE
IRQACK
0 0
Chapter 4 Interrupt
Section/
Access Reset value
R/W 00h 4.4.1/63
2 1
0
IRQIE IRQMOD
0 0
page
0
0
63