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Memory map and register definition
Field
0
Bus clock to the MTIM module is disabled.
1
Bus clock to the MTIM module is enabled.
4
PWT1 Clock Gate Control
PWT1
This bit controls the clock gate to the PWT1 module.
0
Bus clock to the PWT1 module is disabled.
1
Bus clock to the PWT1 module is enabled.
3
PWT0 Clock Gate Control
PWT0
This bit controls the clock gate to the PWT0 module.
0
Bus clock to the PWT0 module is disabled.
1
Bus clock to the PWT0 module is enabled.
2
SCI Clock Gate Control
SCI
This bit controls the clock gate to the SCI module.
0
Bus clock to the SCI module is disabled.
1
Bus clock to the SCI module is enabled.
1
FTM Clock Gate Control
FTM
This bit controls the clock gate to the FTM module.
0
Bus clock to the FTM module is disabled.
1
Bus clock to the FTM module is enabled.
0
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
9.8.15 System Clock Divider Register (SIM_SCDIV)
This register sets the divide value for the clock.
Address: 1800h base + Fh offset = 180Fh
Bit
7
Read
0
Write
Reset
0
Field
7–6
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
5
Clock 1 output divider value
DIV1
This field sets the divide value for the core/system clock.
120
SIM_SCGC3 field descriptions (continued)
6
5
DIV1
0
1
SIM_SCDIV field descriptions
Table continues on the next page...
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Description
4
3
0
DIV2
0
0
Description
2
1
0
DIV3
0
0
NXP Semiconductors
0
0
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