Receiver Functional Description - NXP Semiconductors MC9S08SU16 Reference Manual

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Functional description
When idle-line wake-up is used, a full character time of idle (logic 1) is needed between
messages to wake up any sleeping receivers. Normally, a program would wait for
SCI_S1[TDRE] to become set to indicate the last character of a message has moved to
the transmit shifter, then write 0 and then write 1 to the SCI_C2[TE] bit. This action
queues an idle character to be sent as soon as the shifter is available. As long as the
character in the shifter does not finish while SCI_C2[TE] is cleared, the SCI transmitter
never actually releases control of the TxD pin. If there is a possibility of the shifter
finishing while SCI_C2[TE] is cleared, set the general-purpose I/O controls so the pin
shared with TxD is an output driving a logic 1. This ensures that the TxD line looks like a
normal idle line even if the SCI loses control of the port pin between writing 0 and then 1
to SCI_C2[TE].
The length of the break character is affected by the SCI_S2[BRK13] and SCI_C1[M] as
shown below.
BRK13
0
0
0
0
1
1
1
1

22.5.3 Receiver functional description

In this section, the receiver block diagram is a guide for the overall receiver functional
description.
Next, the data sampling technique used to reconstruct receiver data is described in more
detail. Finally, two variations of the receiver wakeup function are explained.
The receiver input is inverted by setting SCI_S2[RXINV]. The receiver is enabled by
setting the SCI_C2[RE] bit. Character frames consist of a start bit of logic 0, eight (or
nine) data bits (lsb first), and one (or two) stop bits of logic 1. For information about 9-bit
data mode, refer to
8- and 9-bit data
the SCI is configured for normal 8-bit data mode.
412
Table 22-4. Break character length
M
0
0
1
1
0
0
1
1
modes. For the remainder of this discussion, assume
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
SBNS
Break character length
0
1
0
1
0
1
0
1
10 bit times
11 bit times
11 bit times
12 bit times
13 bit times
14 bit times
14 bit times
15 bit times
NXP Semiconductors

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