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Memory map/register definition
Field
DATA
Data
In master transmit mode, when data is written to this register, a data transfer is initiated. The most
significant bit is sent first. In master receive mode, reading this register initiates receiving of the next byte
of data.
NOTE: When making the transition out of master receive mode, switch the I2C mode before reading the
In slave mode, the same functions are available after an address match occurs.
The C1[TX] bit must correctly reflect the desired direction of transfer in master and slave modes for the
transmission to begin. For example, if the I2C module is configured for master transmit but a master
receive is desired, reading the Data register does not initiate the receive.
Reading the Data register returns the last byte received while the I2C module is configured in master
receive or slave receive mode. The Data register does not reflect every byte that is transmitted on the I2C
bus, and neither can software verify that a byte has been written to the Data register correctly by reading it
back.
In master transmit mode, the first byte of data written to the Data register following assertion of MST (start
bit) or assertion of RSTA (repeated start bit) is used for the address transfer and must consist of the
calling address (in bits 7-1) concatenated with the required R/W bit (in position bit 0).
21.4.6 I2C Control Register 2 (I2C_C2)
Address: 18B0h base + 5h offset = 18B5h
Bit
7
Read
GCAEN
Write
Reset
0
Field
7
General Call Address Enable
GCAEN
Enables general call address.
0
Disabled
1
Enabled
6
Address Extension
ADEXT
Controls the number of bits used for the slave address.
0
7-bit address scheme
1
10-bit address scheme
5
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
4
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
370
I2C_D field descriptions
Data register to prevent an inadvertent initiation of a master receive data transfer.
6
5
0
ADEXT
0
0
I2C_C2 field descriptions
Table continues on the next page...
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Description
4
3
0
RMEN
0
0
Description
2
1
AD[10:8]
0
0
NXP Semiconductors
0
0
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