Mux Pin Enable Register (Cmp_Muxpe) - NXP Semiconductors MC9S08SU16 Reference Manual

18.10.7 MUX Pin Enable Register (CMP_MUXPE)

This register requests static ownership of a given package pin by the ANMUX. The
MUXPE must be programmed to enable ANMUX ownership of all input pins that may
be required by an application. These fields are in addition to MUXCR[PSEL] and
MUXCR[MSEL], which control "on the fly" switching between inputs.
Address: 68h base + 6h offset = 6Eh
Bit 7
Read
Write
Reset 0
Field
7–3 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
INPE Positive Input Pin Enable
XX1 Input pin P0 is required by the ANMUX.
X1X Input pin P1 is required by the ANMUX.
1XX Input pin P2 is required by the ANMUX.
18.11 CMP Functional Description
The Comparator can be used to compare two analog input voltages applied to INP and
INM. The analog comparator output (CMPO) is high when the non-inverting input is
greater than the inverting input, and is low when the non-inverting input is less than the
inverting input. This signal can be selectively inverted by setting CR1[INV] = 1.
The SCR[IER], SCR[IEF] bits are used to select the condition which will cause the
comparator module to assert an interrupt to the processor. SCR[CFF] is set on a falling
edge and SCR[CFR] is set on rising edge of the comparator output. The (optionally
filtered) comparator output can be read directly through the SCR[COUT] bit.
NXP Semiconductors
6 5
0
0 0
CMP_MUXPE field descriptions
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 18 Chip-specific ACMP information
4 3
0 0
Description
2 1
INPE
0 0
0
0
301