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• ALTCLK, that is, alternate clock which is OSCOUT
• The asynchronous clock (ADACK): This clock is generated from a clock source
within the ADC module. When selected as the clock source, this clock remains active
while the MCU is in Wait or Stop mode and allows conversions in these modes for
lower noise operation.
Whichever clock is selected, its frequency must fall within the specified frequency range
for ADCK. If the available clocks are too slow, the ADC does not perform according to
specifications. If the available clocks are too fast, the clock must be divided to the
appropriate frequency. This divider is specified by the ADC_SC3[ADIV] bits and can be
divide-by 1, 2, 4, or 8.
17.5.2 Hardware trigger
The ADC module has a selectable asynchronous hardware conversion trigger, ADHWT,
that is enabled when the ADC_SC2[ADTRG] bit is set. This source is not available on all
MCUs. See the module introduction for information on the ADHWT source specific to
this MCU.
When ADHWT source is available and hardware trigger is enabled
( ADC_SC2[ADTRG] = 1), a conversion is initiated on the rising edge of ADHWT. If a
conversion is in progress when a rising edge occurs, the rising edge is ignored. In
continuous convert configuration, only the initial rising edge to launch continuous
conversions is observed. The hardware trigger function operates in conjunction with any
of the conversion modes and configurations.
17.5.3 Conversion control
Conversions can be performed in 12-bit mode, 10-bit mode, or 8-bit mode as determined
by the ADC_SC3[MODE] bits. Conversions can be initiated by a software or hardware
trigger. In addition, the ADC module can be configured for low power operation, long
sample time, continuous conversion, and an automatic compare of the conversion result
to a software determined compare value.
17.5.3.1 Initiating conversions
A conversion initiates under the following conditions:
NXP Semiconductors
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 17 Analog-to-digital converter (ADC)
271
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