Functional Description - NXP Semiconductors MC9S08SU16 Reference Manual

PWM source selection is based
on a number of factors:
•
state of current sense pins
•
IPOL bit
•
OUTCTL bit
•
center vs edge aligned
•
PWM counter direction
26.3

Functional description

26.3.1 Prescaler
To permit lower PWM frequencies, the prescaler produces the PWM clock frequency by
dividing the PWM operation clock frequency by one, two, four, or eight. The prescaler
bits, PRSC0 and PRSC1 in the control (CTRL) register, select the prescaler divisor. This
prescaler is buffered and will not be used by the PWM generator until the LDOK bit is
set and a new PWM reload cycle begins.
26.3.2 Generator
The PWM generator contains a 15-bit up/down PWM counter producing output signals
with software selectable alignment, period, duty cycle, and the inversion of PWM signal
generation.
NXP Semiconductors
SWAP01x
Generate Complement
& Insert Deadtime
OUTCTL0
OUT0
1
PWM
Generator
0
PWM
Generator
1
OUT1
1
OUTCTL1
Figure 26-2. PWM SWAP
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 26 Pulse Width Modulator (PWM)
MASK0x
1
INDEP01
1
MASK1x
PAD
FAULT
&
Polarity
Control
PAD
485