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Memory Map and Register Descriptions
Field
0
an invalid fault state on the FAULT3 pin
1
a valid fault state on the FAULT3 pin
6
FAULT3 Flag
FFLAG3
This read-only flag is set within two CPU cycles after a rising edge on the filtered FAULT3 pin. Clear
FFLAG3 by writing a one to the FTACK3 bit in this register (FLTACK). A reset clears FFLAG3.
0
No fault on the FAULT3 pin
1
Fault on the FAULT3 pin
5
FAULT2 Pin
FPIN2
This read-only bit reflects the current state of the filtered FAULT2 pin. A reset has no effect on FPIN2.
0
an invalid fault state on the FAULT2 pin
1
a valid fault state on the FAULT2 pin
4
FAULT2 Flag
FFLAG2
This read-only flag is set within two CPU cycles after a rising edge on the filtered FAULT2 pin. Clear
FFLAG2 by writing a one to the FTACK2 bit in this register (FLTACK). A reset clears FFLAG2.
0
No fault on the FAULT2 pin
1
Fault on the FAULT2 pin
3
FAULT1 Pin
FPIN1
This read-only bit reflects the current state of the filtered FAULT1 pin. A reset has no effect on FPIN1.
0
an invalid fault state on the FAULT1 pin
1
a valid fault state on the FAULT1 pin
2
FAULT1 Flag
FFLAG1
This read-only flag is set within two CPU cycles after a rising edge on the filtered FAULT1 pin. Clear
FFLAG1 by writing a one to the FTACK1 bit in this register (FLTACK). A reset clears FFLAG1.
0
No fault on the FAULT1 pin
1
Fault on the FAULT1 pin
1
FAULT0 Pin
FPIN0
This read-only bit reflects the current state of the filtered FAULT0 pin. A reset has no effect on FPIN0.
0
an invalid fault state on the FAULT0 pin
1
a valid fault state on the FAULT0 pin
0
FAULT0 Flag
FFLAG0
This read-only flag is set within two CPU cycles after a rising edge on the filtered FAULT0 pin. Clear
FFLAG0 by writing a one to the FTACK0 bit in this register (FLTACK). A reset clears FFLAG0.
0
No fault on the FAULT0 pin
1
Fault on the FAULT0 pin
512
PWM_FLTACKH field descriptions (continued)
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Description
NXP Semiconductors
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