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Memory map and register definition
8.5 Memory map and register definition
Absolute
address
(hex)
0
Port A Data Register (PORT_PTAD)
1
Port B Data Register (PORT_PTBD)
2
Port C Data Register (PORT_PTCD)
3
Port A Direction Register (PORT_PTADD)
4
Port B Direction Register (PORT_PTBDD)
5
Port C Direction Register (PORT_PTCDD)
18E0
Port A Pullup Enable Register (PORT_PTAPE)
18E1
Port B Pullup/Pulldown Enable Register (PORT_PTBPE)
18E2
Port C Pullup Enable Register (PORT_PTCPE)
Port B High Drive Strength Selection Register
18E6
(PORT_PTBHD)
18EC
Port Clock Division Register (PORT_FCLKDIV)
18ED
Port Filter Register 0 (PORT_IOFLT0)
18EE
Port Filter Register 1 (PORT_IOFLT1)
18EF
Port Filter Register 2 (PORT_IOFLT2)
8.5.1 Port A Data Register (PORT_PTAD)
Reading and writing of parallel I/O is accomplished through this register.
When a digital peripheral module or system function is selected and enabled on a pin,
reads of this register still returns the pin value of the associated pin if PORT_PTADD[n]
= 0. (n=0-7) When a shared analog function is selected for a pin, all digital pin functions
are disabled. A read of this register returns a value of 0 for any bits that have shared
analog functions enabled.
A write of valid data to this register must occur before setting the direction control bit of
an associated port pin. This ensures that the pin will not be driven with an incorrect data
value.
Address: 0h base + 0h offset = 0h
Bit
7
Read
Write
Reset
0
86
PORT memory map
Register name
6
5
0
0
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Width
Access
(in bits)
8
R/W
8
R/W
8
R/W
8
R/W
8
R/W
8
R/W
8
R/W
8
R/W
8
R/W
8
R/W
8
R/W
8
R/W
8
R/W
8
R/W
4
3
PTAD
0
0
Section/
Reset value
page
00h
8.5.1/86
00h
8.5.2/87
00h
8.5.3/87
00h
8.5.4/88
00h
8.5.5/89
00h
8.5.6/89
00h
8.5.7/90
00h
8.5.8/91
00h
8.5.9/91
00h
8.5.10/92
00h
8.5.11/92
00h
8.5.12/93
00h
8.5.13/94
00h
8.5.14/95
2
1
0
0
NXP Semiconductors
0
0
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