Fll Engaged Internal (Fei); Fll Engaged External (Fee); Block Diagram - NXP Semiconductors MC9S08SU16 Reference Manual

Introduction

12.1.2 Block diagram

The following figure is the ICS block diagram.
External Reference Clock /
Internal
Reference
Clock
SCFTRIMSCTRIM
IREFST
Figure 12-1. Internal clock source (ICS) block diagram
12.1.3 Modes of operation
There are seven modes of operation for the ICS: FEI, FEE, FBI, FBILP, FBE, FBELP,
and STOP. Each of these modes is explained briefly in the following subsections.

12.1.3.1 FLL engaged internal (FEI)

In FLL engaged internal mode, which is the default mode, the ICS supplies a clock
derived from the FLL which is controlled by the internal reference clock.

12.1.3.2 FLL engaged external (FEE)

In FLL engaged external mode, the ICS supplies a clock derived from the FLL which is
controlled by an external reference clock source.
190
Oscillator
Internal Clock Source Block
LP
n
2 Filter
/
n=0-7
IREFS
RDIV
CLKST LOLIE LOLS
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
IRCLKEN
BDIV
n=0-7
CLKS
FLL
ICSLCLK
DCOOUT
DCO 2
LOCK CME
ICSIRCLK
n
/ 2
ICSOUT
ICSBDCCLK
CLKSW
MSTRCLK
ICSFFCLK
NXP Semiconductors