Memory Map And Register Descriptions - NXP Semiconductors MC9S08SU16 Reference Manual

The width of pulse output is between one and two clocks.
To use the I/O trigger to trig the PDB, the user needs to open
the I/O filter in advance.
23.6

Memory Map and Register Descriptions

Absolute
address
(hex)
60 PDB Control Register 0 (PDB_CTRL0)
61 PDB Control Register 1 (PDB_CTRL1)
62 PDB0 Comparison Low Register (PDB_CMPL0)
63 PDB0 Comparison High Register (PDB_CMPH0)
64 PDB0 Counter High/Low (PDB_CNT0)
65 PDB1 Comparison Low Register (PDB_CMPL1)
66 PDB1 Comparison High Register (PDB_CMPH1)
67 PDB1 Counter High/Low (PDB_CNT1)
23.6.1 PDB Control Register 0 (PDB_CTRL0)
Address: 60h base + 0h offset = 60h
Bit 7
Read TCF1
Write w1c
Reset 0
Field
7 PDB1 Timer Compare Flag
TCF1
This bit is set when a successful compare occurs. Clear this bit by writing one to it.
6 PDB1 Timer Compare Interrupt Enable
TCIE1
0 Timer compare interrupt requests disabled.
1 Timer compare interrupt requests enabled.
5 PDB1 Trigger Output
TRGOUT1
Configure PDB1 trigger output as an pulse or level when a successful compare occurs.
NXP Semiconductors
NOTE
PDB memory map
Register name
6 5
TCIE1 TRGOUT1
0 0
PDB_CTRL0 field descriptions
Table continues on the next page...
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 23 Programmable Delay Block (PDB)
Width
(in bits)
8
8
8
8
8
8
8
8
4 3
TCF0
MOD1
w1c
0 0
Description
Section/
Access Reset value
R/W 00h 23.6.1/425
R/W 00h 23.6.2/426
R/W FFh 23.6.3/427
R/W FFh 23.6.4/428
R/W 00h 23.6.5/428
R/W FFh 23.6.6/429
R/W FFh 23.6.7/429
R/W 00h 23.6.8/430
2 1
TCIE0 TRGOUT0
0 0
page
0
MOD0
0
425