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Memory map and register definition
14.7.6 Low Voltage Control and Status Register 1 (system 5 V)
(PMC_LVCTLSTAT1)
Address: 1850h base + 5h offset = 1855h
Bit
7
Read
Write
Reset
0
POR
0
Field
7–5
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
4
Low Voltage Warning (LVW) Flag for VDDX
SLVWF
This read-only status bit indicates a low voltage warning event. SLVWF is set when V
below the trip point, or after reset and V
reset. Therefore, to use the LVW interrupt function, before enabling SLVWIE, SLVWF must be cleared by
writing SLVWACK first.
0
Low voltage warning event is not detected.
1
Low voltage warning event is detected.
3
Low Voltage Warning Acknowledge
SLVWACK
This write-only bit is used to acknowledge low voltage warning errors. Write 1 to clear SLVWF. Reading
always returns 0.
2
Low Voltage Warning Interrupt Enable
SLVWIE
Enables hardware interrupt requests for SLVWF.
0
Hardware interrupt disabled (use polling).
1
Request a hardware interrupt when SLVWF = 1.
1
Low Voltage Warning Selection
SLVWSEL
0
4.2 V LVW threshold selected.
1
3.7 V LVW threshold selected.
0
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
226
6
5
0
SLVWF
0
0
0
0
PMC_LVCTLSTAT1 field descriptions
Supply
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
4
3
SLVWIE
SLVWACK
0
0
1
0
Description
is already below V
. SLVWF is set to 1 after power-on
LVW
2
1
SLVWSEL
0
0
0
0
transitions
Supply
NXP Semiconductors
0
0
0
0
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