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When configuring I2C to use "SDA(PTA5) and SCL(PTA4)"
pins, and if an application uses internal pullups instead of
external pullups, the internal pullups remain present setting
when the pins are configured as outputs, but they are
automatically disabled to save power when the output values
are low.
8.4 Input glitch filter
A filter is implemented for each port pin that is configured as a digital input. It can be
used as a simple low-pass filter to filter any glitch that is introduced from the pins of PTx
(x=A,B, or C), I2C, PWT, XBI, RESET, and KBI. The glitch width threshold can be
adjusted easily by setting registers PORT_IOFLTn (n=0–2) and PORT_FCLKDIV
between 1–4096 BUSCLKs (or 1–128 LPOCLKs). This configurable glitch filter can
take the place of an on board external analog filter, and greatly improve the EMC
performance because any glitch will not be wrongly sampled or ignored.
Setting register PORT_IOFLTn (n=0–2) can configure the filter of the whole port. For
example, setting PORT_IOFLT0[FLTA] affects all PTA pins.
Glitches that are shorter than the selected clock period are filtered out; Glitches that are
twice more than the selected clock period are filtered out. It passes to internal circuitry.
Pass to
internal rate
100%
0
Note: FLTxxx is contents in register PORT_IOFLTn (n=0-2).
NXP Semiconductors
NOTE
1(FLTxxx period)
2(FLTxxx period)
Figure 8-2. Input glitch filter
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 8 Port Control (PORT)
Input high/low width
85
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