NXP Semiconductors MC9S12ZVMB-Family Manuals

NXP Semiconductors MC9S12ZVMB-Family Manuals

Manuals and User Guides for NXP Semiconductors MC9S12ZVMB-Family. We have 1 NXP Semiconductors MC9S12ZVMB-Family manual available for free PDF download: Reference Manual

NXP Semiconductors MC9S12ZVMB-Family Reference Manual

NXP Semiconductors MC9S12ZVMB-Family Reference Manual (758 pages)

Brand: NXP Semiconductors | Category: Microcontrollers | Size: 3 MB

Table of Contents

Table of Contents
3
Introduction
17
Features
18
Chapter 1 ADC Module Versions

19
- Module Features
  20
- Device Memory Map
  28
  - Part ID Assignments
    31
  - Power Supply Pins
    37
  - Package and Pinouts
    39
  - Pin and Signal Mapping Overview
    41
- Internal Signal Mapping
  44
- Security
  49
  - Operation of the Secured Microcontroller
    50
  - Reprogramming the Security Bits
    51
  - Interrupt Vectors
    52
  - Effects of Reset
    55
  - Flash IFR Mapping
    56
  - Application Information
    57
  - SCI Baud Rate Detection
    60
  - Power Domain Considerations
    63
Chapter 2

67
- Introduction
  68
- Features
  70
- External Signal Description
  71
- Internal Routing Options
  76
- Register Map
  77
- PIM Registers 0X0200-0X020F
  82
- PIM Generic Registers
  91
- PIM Generic Register Exceptions
  97
- Functional Description
  106
- Pin I/O Control
  107
- Pull Devices
  108
- High-Voltage Input
  110
- Initialization and Application Information
  112
  - Over-Current Protection on PP0 (EVDD)
    113
    
    Introduction
    117
    
    Glossary
    118
    
    Block Diagram
    119
    
    Register Descriptions
    120
    
    Functional Description
    125
Chapter 3

127
- Illegal Accesses
  127
- Uncorrectable ECC Faults
  128
- Introduction
  129
Chapter 6

130
- Glossary
  130
  - Modes of Operation
    131
  - External Signal Description
    132
  - Register Descriptions
    133
  - Functional Description
    137
Chapter 4

138
- S12Z Exception Requests
  138
- Priority Decoder
  139
- Interrupt Vector Table Layout
  140
- Wake up from Stop or Wait Mode
  141
  - Introduction
    143
  - Glossary
    144
  - Block Diagram
    147
  - Memory Map and Register Definition
    148
  - Functional Description
    152
Chapter 5

153
- Clock Source
  153
- BDC Access of Internal Resources
  170
- BDC Serial Interface
  173
- Serial Interface Hardware Handshake (ACK Pulse) Protocol
  176
- Hardware Handshake Abort Procedure
  178
- Hardware Handshake Disabled (ACK Pulse Disabled)
  179
- Single Stepping
  180
- Serial Communication Timeout
  181
  - Introduction
    183
  - Glossary
    184
  - Modes of Operation
    185
  - Memory Map and Registers
    186
  - Register Descriptions
    188
  - Functional Description
    200
- Comparator Modes
  201
- Events
  204
- State Sequence Control
  206
- Application Information
  207
- Breakpoints from Other S12Z Sources
  208
  - Introduction
    209
  - Memory Map and Register Definition
    210
  - Register Descriptions
    212
  - Functional Description
    216
Chapter 7

217
- Aligned Memory Write Access
  217
- Memory Read Access
  218
- ECC Algorithm
  219
  - Introduction
    221
  - Features
    222
  - Modes of Operation
    224
Chapter 8

227
- S12CPMU_UHV_V11 Block Diagram
  227
  - Signal Description
    229
  - BCTL — Base Control Pin for External PNP
    230
  - Memory Map and Registers
    231
  - Register Descriptions
    233
  - Functional Description
    273
- Startup from Reset
  275
- Stop Mode Using PLLCLK as Source of the Bus Clock
  276
- External Oscillator
  278
- System Clock Configurations
  279
- Resets
  280
- Description of Reset Operation
  281
- PLL Clock Monitor Reset
  282
- Power-On Reset (POR)
  283
- Interrupts
  284
- Initialization/Application Information
  286
Chapter 9

289
- Differences ADC12B_LBA V1 Vs V2 Vs V3
  289
- Introduction
  290
- Key Features
  291
  - Modes of Operation
    292
  - Block Diagram
    295
- Signal Description
  296
  - Memory Map and Register Definition
    297
  - Register Descriptions
    300
  - Functional Description
    334
  - Digital Sub-Block
    335
  - Resets
    348
  - ADC Error and Conversion Flow Control Issue Interrupt
    349
- Use Cases and Application Information
  350
- Memory Map and Register Definition
  361
  - Functional Description
    365
  - Introduction
    369
  - Block Diagrams
    370
  - External Signal Description
    371
  - Functional Description
    383
  - Prescaler
    384
Chapter 10

385
Chapter 11

385
- Input Capture
  385
- Resets
  386
Chapter 12

387
- Introduction
  388
Chapter 18

389
- Features
  389
- Block Diagram
  390
- Signal Descriptions
  391
- Commutation Event Edge Select Signal — Async_Event_Edge_Sel[1:0]
  392
- Memory Map and Registers
  393
  - Register Descriptions
    398
  - Functional Description
    426
  - Prescaler
    427
  - Independent or Complementary Channel Operation
    431
  - Deadtime Generators
    432
  - Top/Bottom Correction
    434
  - Asymmetric PWM Output
    440
  - Variable Edge Placement PWM Output
    441
  - Double Switching PWM Output
    442
  - Output Polarity
    444
  - PWM Generator Loading
    447
  - Fault Protection
    452
- Resets
  454
  - Interrupts
    455
  - BLDC 6-Step Commutation
    456
    
    Introduction
    459
    
    Block Diagram
    460
    
    PTURE — PTUE Reload Event
    461
    
    Register Descriptions
    462
    
    Functional Description
    473
  - Memory Based Trigger Event List
    474
  - Reload Mechanism
    475
  - Async Reload Event
    476
  - Debugging
    478
  - Introduction
    479
  - Features
    480
  - Modes of Operation
    481
  - TXD — Transmit Pin
    482
- Functional Description
  493
Chapter 14

494
- Infrared Interface Submodule
  494
- LIN Support
  495
- Baud Rate Generation
  496
- Transmitter
  498
- Receiver
  503
- Single-Wire Operation
  511
- Loop Operation
  512
- Modes of Operation
  513
- Recovery from Wait Mode
  515
- Introduction
  517
  - Block Diagram
    518
- External Signal Description
  519
  - MISO — Master In/Slave out Pin
    520
  - Register Descriptions
    521
- Functional Description
  529
- Master Mode
  530
Chapter 15

531
- Slave Mode
  531
- Transmission Formats
  532
- SPI Baud Rate Generation
  537
- Special Features
  538
- Error Conditions
  539
- Low Power Mode Options
  540
- Introduction
  543
  - Modes of Operation
    544
- External Signal Description
  545
  - Module Memory Map
    546
Chapter 16

547
- Register Definition
  547
- HSDRV2C Slew Rate Control Register (HSSLR)
  549
- Reserved Register
  550
- HSDRV2C Status Register (HSSR)
  551
- HSDRV2C Interrupt Flag Register (HSIF)
  552
- Over-Current Shutdown
  553
  - Introduction
    555
  - Modes of Operation
    556
  - Block Diagram
    557
  - LIN — LIN Bus Pin
    558
  - Register Descriptions
    559
  - Functional Description
    565
- Modes
  566
- Interrupts
  569
- Application Information
  572
  - Introduction
    575
  - Block Diagram
    577
  - External Signal Description
    578
Chapter 17 Memory Map and Register Definition

579
- Register Summary
  580
  - Register Descriptions
    581
  - Functional Description
    595
- High-Side FET Pre-Driver
  596
- Charge Pump
  598
- Desaturation Error
  599
- Phase Comparators
  600
- Fault Protection Features
  601
- Current Sense Amplifier and Overcurrent Comparator
  605
- Interrupts
  606
- Application Information
  607
- GDU Intrinsic Dead Time
  608
- Introduction
  613
Chapter 19

614
- Glossary
  614
  - Block Diagram
    615
  - External Signal Description
    617
  - Memory Map and Registers
    618
  - Register Descriptions
    622
  - Functional Description
    642
- Internal NVM Resource
  643
- Flash Command Operations
  644
- Allowed Simultaneous P-Flash and EEPROM Operations
  648
- Flash Command Description
  649
- Interrupts
  665
- Wait Mode
  666
- Unsecuring the MCU in Special Single Chip Mode Using BDM
  667
Appendix A

669
- A.1 General
  669
- A.2 I/O Pin Characteristics
  679
- A.3 Supply Currents
  681
Appendix B

685
Appendix C

691
- C.1 ADC Operating Characteristics
  691
Appendix D

697
- D.1 Maximum Ratings
  697
- D.3 Dynamic Electrical Characteristics
  698
Appendix E

701
- E.1 Operating Characteristics
  701
  - F.1 Operating Characteristics
    705
  - F.3 Dynamic Characteristics
    707
Appendix F

709
Appendix G

709
- G.1 NVM Timing Parameters
  709
- G.2 NVM Reliability Parameters
  710
- G.3 NVM Factory Shipping Condition
  711
Appendix H

713
- H.1 Static Electrical Characteristics
  713
- H.2 Dynamic Electrical Characteristics
  714
Appendix I Appendix K

724
Appendix L

725
- L.1 0X0000–0X0003 Part ID
  725
- L.3 0X0070-0X00Ff S12ZMMC
  727
- L.6 0X0380-0X039F FTMRZ
  735
- L.7 0X03C0-0X03Cf SRAM_ECC_32D7P
  737
- L.8 0X0400-0X042F TIM1
  738
- L.9 0X0500-X053F PMF15B6C
  740
- L.10 0X0580-0X059F PTU
  743
- L.11 0X05C0-0X05Ef TIM0
  745
- L.12 0X0600-0X063F ADC0
  747
- L.13 0X06A0-0X06Bf GDU
  748
- L.14 0X06C0-0X06Df CPMU
  750
- L.15 0X06F0-0X06F7 BATS
  751
- L.16 0X0700-0X0707 SCI0
  752
- L.17 0X0710-0X0717 SCI1
  753
- L.19 0X0980-0X0987 LINPHY0
  754

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