Gcmp Interrupts - NXP Semiconductors MC9S08SU16 Reference Manual

GCMP interrupts

The values of FPR[FILT_PER] (or SAMPLE period) and CR0[FILTER_CNT] must also
be traded off against the desire for minimal latency in recognizing actual comparator
output transitions. The probability of detecting an actual output change within the
nominal latency is the probability of a correct sample raised to the CR0[FILTER_CNT]
power.
Table 25-3. Comparator Sample/Filter Maximum Latencies
CR1[ CR1[ CR1[
Mode #
EN] WE]
1 0 X
2A 1 0
2B 1 0
3A 1 0
3B 1 0
4A 1 0
4B 1 0
5A 1 1
5B 1 1
6 1 1
7 1 1
1. T represents the intrinsic delay of the analog component plus the polarity select logic. T
PD
external sample clock. T
25.8 GCMP interrupts
The GCMP module is capable of generating an interrupt on either the rising or falling
edge of the comparator output (or both). The interrupt request is asserted when both
SCR[IER] bit and SCR[CFR] are set. It is also asserted when both SCR[IEF] bit and
SCR[CFF] are set. The interrupt is de-asserted by clearing either SCR[IER] or
SCR[CFR] for a rising edge interrupt, or SCR[IEF] and SCR[CFF] for a falling edge
interrupt.
480
CR0[FILTER FPR[FILT_P
SE] _CNT] ER]
X X
0 0x00
0 X 0x00
1 0x01
0 0x01 > 0x00
1 > 0x01
0 > 0x01 > 0x00
0 0x00
0 X 0x00
0 0x01 0x01 - 0xFF
0 > 0x01 0x01 - 0xFF
is the period of the bus clock.
per
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Operation
X Disabled
X Continuous Mode
X Sampled, Non-Filtered mode
X Sampled, Filtered mode
X Windowed mode
Windowed / Resampled
mode
Windowed / Filtered mode
1
Maximum Latency
N/A
T
PD
T + T + T
PD SAMPLE per
T + (FPR[FILT_PER] x
PD
T ) + T
per per
T + (CR0[FILTER_CNT] x
PD
T ) + T
SAMPLE per
T + (CR0[FILTER_CNT] x
PD
FPR[FILT_PER] x T ) + T
per
T + T
PD per
T + T
PD per
T + (FPR[FILT_PER] x
PD
T ) + 2T
per per
T + (CR0[FILTER_CNT] x
PD
FPR[FILT_PER] x T ) +
per
2T
per
is the clock period of the
SAMPLE
NXP Semiconductors
per