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4 bit
Prescaler
23.5
Mode of operation
23.5.1 Single shot delay mode
In the single shot delay mode:
1. Trigger pulse ( include both HW and SW trigger) clear output and start counter from
zero
2. Before counter reaches compare value, new trigger will restart counter from zero
3. When counter value is equal and greater than compare value, counter stops and
output set to high
4. If Pulse output mode is set, pulse will be generated when counter value is equal and
greater than compare value
5. A stop bit is needed to stop counter and reset counter to zero and clear output.
NXP Semiconductors
16bit Compare Value B
16 bit Counter B
Counter trigger
From Crossbar
Output
16bit Compare Value A
16 bit Counter A
Counter Trigger
From Crossbar
Output
Figure 23-1. PDB block diagram
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 23 Programmable Delay Block (PDB)
>=
S top and Reset Counter
Or Reset Counter
>=
S top and Reset Counter
Or Reset Counter
Interrupt
T o Crossbar
S et
Input
Q
Clear
Interrupt
S et
Q
T o Crossbar
Input
Clear
423
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