Automatic Fault Clearing - NXP Semiconductors MC9S08SU16 Reference Manual

26.3.9.2 Automatic fault clearing

In automatic mode, when FMODEn is set, disabled PWM pins are enabled when the
FAULTn pin returns to 0 and a new PWM half cycle begins. Please refer to the following
figure. Clearing the FFLAGn flag does not affect disabled PWM pins when FMODEn is
set.
PWM Output
Fault Input
26.3.9.3 Manual fault clearing
In manual mode, the fault pins are grouped in pairs, each pair sharing common
functionality. A fault condition on Fault pins 0 and 2 can be cleared by software clearing
the corresponding FFLAG bit, allowing the PWM(s) to enable at the next PWM half
cycle regardless of the logic level at the fault pin. The PWM outputs will remain enabled
even if the logic level of the fault pin is still high. The fault pin must go low and then
back high to register a new fault and disable the PWM outputs. Figure 1-30. A fault
condition on fault pins 1 and 3 can be cleared only by software clearing corresponding
FFLAGn bit, allowing the PWM(s) to enable if a logic low at the fault pin is detected at
the start of the next PWM half cycle boundary. Please see Figure 1-31.
Fault 0
or Fault 2
NXP Semiconductors
PWM Enabled
Figure 26-29. Automatic fault clearing
PWMS Enabled PWMS Disabled
FFLAGn
Cleared
Figure 26-30. Manual fault clearing (example 1)
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 26 Pulse Width Modulator (PWM)
Disabled Enabled PWM Disabled
PWMS Enabled
PWM Enabled
PWMS Disabled
503