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Functional description
28.4.5.4 Reading data from FIFO
The data stored in the FIFO can be read using BDM commands provided the DBG
module is enabled and not armed (DBG_C[DBGEN] = 1 and DBG_C[ARM] = 0). The
FIFO data is read out first-in-first-out. By reading the DBG_CNT[CNT] bits at the end of
a trace run, the number of valid words can be determined. The FIFO data is read by
optionally reading the DBG_FH register followed by the DBG_FL register. Each time the
DBG_FL register is read, the FIFO is shifted to allow reading of the next word, however,
the count does not decrement. In event-only trigger modes where the FIFO will contain
only the data bus values stored, to read the FIFO only DBG_FL needs to be accessed.
The FIFO is normally read only while DBG_C[ARM] = 0 and DBG_S[ARMF] = 0,
however, reading the FIFO while the DBG module is armed will return the data value in
the oldest location of the FIFO and the TBC will not allow the FIFO to shift. This action
could cause a valid entry to be lost because the unexpected read blocked the FIFO
advance.
If the DBG module is not armed and the DBG_FL register is read, the TBC will store the
current opcode address. Through periodic reads of the DBG_FH and DBG_FL registers
while the DBG module is not armed, host software can provide a histogram of program
execution This is called profile mode.
28.4.6 Interrupt priority
When DBG_T[TRGSEL] is set and the DBG module is armed to trigger on begin- or
end-trigger types, a trigger is not detected in the condition where a pending interrupt
occurs at the same time that a target address reaches the top of the instruction pipe. In
these conditions, the pending interrupt has higher priority and code execution switches to
the interrupt service routine.
When DBG_T[TRGSEL] is clear and the DBG module is armed to trigger on end-trigger
types, the trigger event is detected on a program fetch of the target address, even when an
interrupt becomes pending on the same cycle. In these conditions, the pending interrupt
has higher priority, the exception is processed by the core and the interrupt vector is
fetched. Code execution is halted before the first instruction of the interrupt service
routine is executed. In this scenario, the DBG module will have cleared DBG_C[ARM]
without having recorded the change-of-flow that occurred as part of the interrupt
exception. Note that the stack will hold the return addresses and can be used to
reconstruct execution flow in this scenario.
When DBG_T[TRGSEL] is clear and the DBG module is armed to trigger on begin-
trigger types, the trigger event is detected on a program fetch of the target address, even
when an interrupt becomes pending on the same cycle. In this scenario, the FIFO captures
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
574
NXP Semiconductors
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