I2C Control Register 1 (I2C_C1) - NXP Semiconductors MC9S08SU16 Reference Manual

Memory map/register definition
Field
The SDA hold time is the delay from the falling edge of SCL (I2C clock) to the changing of SDA (I2C data).
SDA hold time = I2C module clock period (s) × mul × SDA hold value
The SCL start hold time is the delay from the falling edge of SDA (I2C data) while SCL is high (start
condition) to the falling edge of SCL (I2C clock).
SCL start hold time = I2C module clock period (s) × mul × SCL start hold value
The SCL stop hold time is the delay from the rising edge of SCL (I2C clock) to the rising edge of SDA (I2C
data) while SCL is high (stop condition).
SCL stop hold time = I2C module clock period (s) × mul × SCL stop hold value
For example, if the I2C module clock speed is 8 MHz, the following table shows the possible hold time
values with different ICR and MULT selections to achieve an I
MULT

21.4.3 I2C Control Register 1 (I2C_C1)

Address: 18B0h base + 2h offset = 18B2h
Bit 7
Read
IICEN
Write
Reset
0
Field
7 I2C Enable
IICEN
Enables I2C module operation.
0 Disabled
1 Enabled
6 I2C Interrupt Enable
IICIE
Enables I2C interrupt requests.
366
I2C_F field descriptions (continued)
ICR
2h 00h
1h 07h
1h 0Bh
0h 14h
0h 18h
6 5
IICIE MST
0 0
I2C_C1 field descriptions
Table continues on the next page...
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Description
2
C baud rate of 100 kbit/s.
Hold times (μs)
SDA SCL Start
3.500
2.500
2.250
2.125
1.125
4 3
TX TXAK
RSTA
0 0
Description
SCL Stop
3.000 5.500
4.000 5.250
4.000 5.250
4.250 5.125
4.750 5.125
2 1
0
WUEN
0 0
NXP Semiconductors
0
0
0